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datasheet rl78/g13 renesas mcu true low power platform (as low as 66 a/mhz, and 0.57 a for rtc + lvd), 1.6 v to 5.5 v operation, 16 to 512 kbyte flash, 41 dmips at 32 mhz, for general purpose applications page 1 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 r01ds0131ej0330 rev.3.30 mar 31, 2016 1. outline 1.1 features ultra-low power consumption technology ? v dd = single power supply voltage of 1.6 to 5.5 v ? halt mode ? stop mode ? snooze mode rl78 cpu core ? cisc architecture with 3-stage pipeline ? minimum instruction execution time: can be changed from high speed (0.03125 s: @ 32 mhz operation with high-speed on-chip oscillator) to ultra-low speed (30.5 s: @ 32.768 khz operation with subsystem clock) ? address space: 1 mb ? general-purpose registers: (8-bit register 8) 4 banks ? on-chip ram: 2 to 32 kb code flash memory ? code flash memory: 16 to 512 kb ? block size: 1 kb ? prohibition of block erase and rewriting (security function) ? on-chip debug function ? self-programming (with boot swap function/flash shield window function) data flash memory ? data flash memory: 4 kb to 8 kb ? back ground operation (bgo): instructions can be executed from the program memory while rewriting the data flash memory. ? number of rewrites: 1,000,000 times (typ.) ? voltage of rewrites: v dd = 1.8 to 5.5 v high-speed on-chip oscillator ? select from 32 mhz, 24 mhz, 16 mhz, 12 mhz, 8 mhz, 6 mhz, 4 mhz, 3 mhz, 2 mhz, and 1 mhz ? high accuracy: +/- 1.0 % (v dd = 1.8 to 5.5 v, t a = -20 to +85c) operating ambient temperature ? t a = -40 to +85c (a: consumer applications, d: industrial applications ) ? t a = -40 to +105c (g: industrial applications) power management and reset function ? on-chip power-on-reset (por) circuit ? on-chip voltage detector (lvd) (select interrupt and reset from 14 levels) dma (direct memory access) controller ? 2/4 channels ? number of clocks during transfer between 8/16-bit sfr and internal ram: 2 clocks multiplier and divider/multiply-accumulator ? 16 bits 16 bits = 32 bits (unsigned or signed) ? 32 bits 32 bits = 32 bits (unsigned) ? 16 bits 16 bits + 32 bits = 32 bits (unsigned or signed) serial interface ? csi: 2 to 8 channels ? uart/uart (lin-bus supported): 2 to 4 channels ? i 2 c/simplified i 2 c communication: 2 to 8 channels timer ? 16-bit timer: 8 to 16 channels ? 12-bit interval timer: 1 channel ? real-time clock: 1 channel (calendar for 99 years, alarm function, and clock correction function) ? watchdog timer: 1 channel (operable with the dedicated low-speed on-chip oscillator) a/d converter ? 8/10-bit resolution a/d converter (v dd = 1.6 to 5.5 v) ? analog input: 6 to 26 channels ? internal reference voltage (1.45 v) and temperature sensor note 1 i/o port ? i/o port: 16 to 120 (n-ch open drain i/o [withstand voltage of 6 v]: 0 to 4, n-ch open drain i/o [v dd withstand voltage note 2 /ev dd withstand voltage note 3 ]: 5 to 25) ? can be set to n-ch open drain, ttl input buffer, and on-chip pull-up resistor ? different potential interface: can connect to a 1.8/2.5/3 v device ? on-chip key interrupt function ? on-chip clock output/buzzer output controller others ? on-chip bcd (binary-coded decimal) correction circuit notes 1. can be selected only in hs (high-speed main) mode 2. products with 20 to 52 pins 3. products with 64 to 128 pins remark the functions mounted depend on the product. see 1.6 outline of functions.
rl78/g13 1. outline page 2 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 ? rom, ram capacities rl78/g13 flash rom data flash ram 20 pins 24 pins 25 pins 30 pins 32 pins 36 pins 8 kb ? ? ? r5f100ag r5f100bg r5f100cg 128 kb ? 12 kb ? ? ? r5f101ag r5f101bg r5f101cg 8 kb ? ? ? r5f100af r5f100bf r5f100cf 96 kb ? 8 kb ? ? ? r5f101af r5f101bf r5f101cf 4 kb r5f1006e r5f1007e r5f1008e r5f100ae r5f100be r5f100ce 64 kb ? 4 kb note r5f1016e r5f1017e r5f1018e r5f101ae r5f101be r5f101ce 4 kb r5f1006d r5f1007d r5f1008d r5f100ad r5f100bd r5f100cd 48 kb ? 3 kb note r5f1016d r5f1017d r5f1018d r5f101ad r5f101bd r5f101cd 4 kb r5f1006c r5f1007c r5f1008c r5f100ac r5f100bc r5f100cc 32 kb ? 2 kb r5f1016c r5f1017c r5f1018c r5f101ac r5f101bc r5f101cc 4 kb R5F1006A r5f1007a r5f1008a r5f100aa r5f100ba r5f100ca 16 kb ? 2 kb r5f1016a r5f1017a r5f1018a r5f101aa r5f101ba r5f101ca rl78/g13 flash rom data flash ram 40 pins 44 pins 48 pins 52 pins 64 pins 80 pins 100 pins 128 pins 8 kb ? r5f100fl r5f100gl r5f100jl r5f100ll r5f100ml r5f100pl r5f100sl 512 kb ? 32 kb note ? r5f101fl r5f101gl r5f101jl r5f101ll r5f101ml r5f101pl r5f101sl 8 kb ? r5f100fk r5f100gk r5f100jk r5f100lk r5f100mk r5f100pk r5f100sk 384 kb ? 24 kb ? r5f101fk r5f101gk r5f101jk r5f101lk r5f101mk r5f101pk r5f101sk 8 kb ? r5f100fj r5f100gj r5f100jj r5f100lj r5f100mj r5f100pj r5f100sj 256 kb ? 20 kb note ? r5f101fj r5f101gj r5f101jj r5f101lj r5f101mj r5f101pj r5f101sj 8 kb r5f100eh r5f100fh r5f100gh r5f100jh r5f100lh r5f100mh r5f100ph r5f100sh 192 kb ? 16 kb r5f101eh r5f101fh r5f101gh r5f101jh r5f101lh r5f101mh r5f101ph r5f101sh 8 kb r5f100eg r5f100fg r5f100gg r5f100jg r5f100lg r5f100mg r5f100pg ? 128 kb ? 12 kb r5f101eg r5f101fg r5f101gg r5f101jg r5f101lg r5f101mg r5f101pg ? 8 kb r5f100ef r5f100ff r5f100gf r5f100jf r5f100lf r5f100mf r5f100pf ? 96 kb ? 8 kb r5f101ef r5f101ff r5f101gf r5f101jf r5f101lf r5f101mf r5f101pf ? 4 kb r5f100ee r5f100fe r5f100ge r5f100je r5f100le ? ? ? 64 kb ? 4 kb note r5f101ee r5f101fe r5f101ge r5f101je r5f101le ? ? ? 4 kb r5f100ed r5f100fd r5f100gd r5f100jd r5f100ld ? ? ? 48 kb ? 3 kb note r5f101ed r5f101fd r5f101gd r5f101jd r5f101ld ? ? ? 4 kb r5f100ec r5f100fc r5f100gc r5f100jc r5f100lc ? ? ? 32 kb ? 2 kb r5f101ec r5f101fc r5f101gc r5f101jc r5f101lc ? ? ? 4 kb r5f100ea r5f100fa r5f100ga ? ? ? ? ? 16 kb ? 2 kb r5f101ea r5f101fa r5f101ga ? ? ? ? ? note the flash library uses ram in self-programmi ng and rewriting of the data flash memory. the target products and start address of the ram areas used by the flash library are shown below. r5f100xd, r5f101xd (x = 6 to 8, a to c, e to g, j, l): start address ff300h r5f100xe, r5f101xe (x = 6 to 8, a to c, e to g, j, l): start address fef00h r5f100xj, r5f101xj (x = f, g, j, l, m, p): start address faf00h r5f100xl, r5f101xl (x = f, g, j, l, m, p, s): start address f7f00h for the ram areas used by the flash library, see self ram list of flash self-programming library for rl78 family (r20ut2944) .
rl78/g13 1. outline page 3 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.2 list of part numbers figure 1-1. part number, memo ry size, and package of rl78/g13 part no. r 5 f 1 0 0 l e a x x x f b #v0 package type: packaging specification rom number (omitted with blank products) rom capacity: rl78/g13 group renesas mcu renesas semiconductor product sp : lsso p, 0.65 mm pitch fp : lfqf p, 0.80 mm pitch #u0 : tray (hwqfn,vfbga,wflga) #v0 : tray (lfqfp,lqfp,lssop) #w0 : embossed tape (hwqfn,vfbga,wflga) #x0 : embossed tape (lfqfp, lqfp, lssop) fa : lfqf p, 0.65 mm pitch fb : lfqf p, 0.50 mm pitch na : hwqfn, 0.50 mm pitch la : wflga, 0.50 mm pitch bg : vfbga, 0.40 mm pitch a : 16 kb c : 32 kb d : 48 kb e : 64 kb f : 96 kb g : 128 kb h : 1 92 kb j : 256 kb k : 384 kb l : 512 kb pin count: 6 : 20-pin 7 : 24-pin 8 : 25-pin a : 30-pin b : 32-pin c : 36-pin e : 40-pin f : 44-pin g : 48-pin j : 52-pin l : 64-pin m : 80-pin p : 100-pin s : 128-pin fields of application: a : consumer applications, operating ambient temperature : -40?c to +85?c d : industrial applications, operating ambient temperature : -40?c to +85?c g : industrial applications, operating ambient temperature : -40?c to +105?c memory type: f : flash memory note 1 note 1 note 2 note 2 note 1 note 1 note 2 note 2 notes 1. products only for ?a: consumer applications (t a = ? 40 to +85c)?, and "g: industrial applications (t a = ? 40 to +105c)" 2. products only for ?a: consumer applications (t a = ? 40 to +85c)?, and "d: industrial applications (t a = ? 40 to +85c)"
rl78/g13 1. outline page 4 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 table 1-1. list of ordering part numbers (1/12) pin count package data flash fields of application note ordering part number mounted a d g R5F1006Aasp#v0, r5f1006casp#v0, r5f1006dasp#v0, r5f1006easp#v0 R5F1006Aasp#x0, r5f1006casp#x0, r5f1006dasp#x0, r5f1006easp#x0 R5F1006Adsp#v0, r5f1006cdsp#v0, r5f1006ddsp#v0, r5f1006edsp#v0 R5F1006Adsp#x0, r5f1006cdsp#x0, r5f1006ddsp#x0, r5f1006edsp#x0 R5F1006Agsp#v0, r5f1006cgsp#v0, r5f1006dgsp#v0, r5f1006egsp#v0 R5F1006Agsp#x0, r5f1006cgsp#x0, r5f1006dgsp#x0, r5f1006egsp#x0 20 pins 20-pin plastic lssop (7.62 mm (300), 0.65 mm pitch) not mounted a d r5f1016aasp#v0, r5f1016casp#v0, r5f1016dasp#v0, r5f1016easp#v0 r5f1016aasp#x0, r5f1016casp#x0, r5f1016dasp#x0, r5f1016easp#x0 r5f1016adsp#v0, r5f1016cdsp#v0, r5f1016ddsp#v0, r5f1016edsp#v0 r5f1016adsp#x0, r5f1016cdsp#x0, r5f1016ddsp#x0, r5f1016edsp#x0 mounted a d g r5f1007aana#u0, r5f1007cana#u0, r5f1007dana#u0, r5f1007eana#u0 r5f1007aana#w0, r5f1007cana#w0, r5f1007dana#w0, r5f1007eana#w0 r5f1007adna#u0, r5f1007cdna#u0, r5f1007ddna#u0, r5f1007edna#u0 r5f1007adna#w0, r5f1007cdna#w0, r5f1007ddna#w0, r5f1007edna#w0 r5f1007agna#u0, r5f1007cgna#u0, r5f1007dgna#u0, r5f1007egna#u0 r5f1007agna#w0, r5f1007cgna#w0, r5f1007dgna#w0, r5f1007egna#w0 24 pins 24-pin plastic hwqfn (4 ? 4mm, 0.5 mm pitch) not mounted a d r5f1017aana#u0, r5f1017cana#u0, r5f1017dana#u0, r5f1017eana#u0 r5f1017aana#w0, r5f1017cana#w0, r5f1017dana#w0, r5f1017eana#w0 r5f1017adna#u0, r5f1017cdna#u0, r5f1017ddna#u0, r5f1017edna#u0 r5f1017adna#w0, r5f1017cdna#w0, r5f1017ddna#w0, r5f1017edna#w0 note for the fields of application, refer to figure 1-1 part number, memory size, and package of rl78/g13 . caution the ordering part numbers represent the numbers at the time of publication. for the latest ordering part numbers, refer to the target product page of the renesas electronics website.
rl78/g13 1. outline page 5 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 table 1-1. list of ordering part numbers (2/12) pin count package data flash fields of application note ordering part number mounted a g r5f1008aala#u0, r5f1008cala#u0, r5f1008dala#u0, r5f1008eala#u0 r5f1008aala#w0, r5f1008cala#w0, r5f1008dala#w0, r5f1008eala#w0 r5f1008agla#u0, r5f1008cgla#u0, r5f1008dgla#u0, r5f1008egla#u0 r5f1008agla#w0, r5f1008cgla#w0, r5f1008dgla#w0, r5f1008egla#w0 25 pins 25-pin plastic wflga (3 ? 3 mm, 0.5 mm pitch) not mounted a r5f1018aala#u0, r5f1018cala#u0, r5f1018dala#u0, r5f1018eala#u0 r5f1018aala#w0, r5f1018cala#w0, r5f1018dala#w0, r5f1018eala#w0 mounted a d g r5f100aaasp#v0, r5f100acasp#v0, r5f100adasp#v0, r5f100aeasp#v0, r5f100afasp#v0, r5f100agasp#v0 r5f100aaasp#x0, r5f100acasp#x0, r5f100adasp#x0 r5f100aeasp#x0, r5f100afasp#x0, r5f100agasp#x0 r5f100aadsp#v0, r5f100acdsp#v0, r5f100addsp#v0, r5f100aedsp#v0, r5f100afdsp#v0, r5f100agdsp#v0 r5f100aadsp#x0, r5f100acdsp#x0, r5f100addsp#x0, r5f100aedsp#x0, r5f100afdsp#x0, r5f100agdsp#x0 r5f100aagsp#v0, r5f100acgsp#v0, r5f100adgsp#v0,r5f100aegsp#v0, r5f100afgsp#v0, r5f100aggsp#v0 r5f100aagsp#x0, r5f100acgsp#x0, r5f100adgsp#x0,r5f100aegsp#x0, r5f100afgsp#x0, r5f100aggsp#x0 30 pins 30-pin plastic lssop (7.62 mm (300), 0.65 mm pitch) not mounted a d r5f101aaasp#v0, r5f101acasp#v0, r5f101adasp#v0, r5f101aeasp#v0, r5f101afasp#v0, r5f101agasp#v0 r5f101aaasp#x0, r5f101acasp#x0, r5f101adasp#x0, r5f101aeasp#x0, r5f101afasp#x0, r5f101agasp#x0 r5f101aadsp#v0, r5f101acdsp#v0, r5f101addsp#v0, r5f101aedsp#v0, r5f101afdsp#v0, r5f101agdsp#v0 r5f101aadsp#x0, r5f101acdsp#x0, r5f101addsp#x0, r5f101aedsp#x0, r5f101afdsp#x0, r5f101agdsp#x0 mounted a d g r5f100baana#u0, r5f100bcana#u0, r5f100bdana#u0, r5f100beana#u0, r5f100bfana#u0, r5f100bgana#u0 r5f100baana#w0, r5f100bcana#w0, r5f100bdana#w0, r5f100beana#w0, r5f100bfana#w0, r5f100bgana#w0 r5f100badna#u0, r5f100bcdna#u0, r5f100bddna#u0, r5f100bedna#u0, r5f100bfdna#u0, r5f100bgdna#u0 r5f100badna#w0, r5f100bcdna#w0, r5f100bddna#w0, r5f100bedna#w0, r5f100bfdna#w0, r5f100bgdna#w0 r5f100bagna#u0, r5f100bcgna#u0, r5f100bdgna#u0, r5f100begna#u0, r5f100bfgna#u0, r5f100bggna#u0 r5f100bagna#w0, r5f100bcgna#w0, r5f100bdgna#w0, r5f100begna#w0, r5f100bfgna#w0, r5f100bggna#w0 32 pins 32-pin plastic hwqfn (5 ? 5 mm, 0.5 mm pitch) not mounted a d r5f101baana#u0, r5f101bcana#u0, r5f101bdana#u0, r5f101beana#u0, r5f101bfana#u0, r5f101bgana#u0 r5f101baana#w0, r5f101bcana#w0, r5f101bdana#w0, r5f101beana#w0, r5f101bfana#w0, r5f101bgana#w0 r5f101badna#u0, r5f101bcdna#u0, r5f101bddna#u0, r5f101bedna#u0, r5f101bfdna#u0, r5f101bgdna#u0 r5f101badna#w0, r5f101bcdna#w0, r5f101bddna#w0, r5f101bedna#w0, r5f101bfdna#w0, r5f101bgdna#w0 note for the fields of application, refer to figure 1-1 part number, memory size, and package of rl78/g13 . caution the ordering part numbers represent the numbers at the time of publication. for the latest ordering part numbers, refer to the target product page of the renesas electronics website.
rl78/g13 1. outline page 6 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 table 1-1. list of ordering part numbers (3/12) pin count package data flash fields of application note ordering part number mounted a g r5f100caala#u0, r5f100ccala#u0, r5f100cdala#u0, r5f100ceala#u0, r5f100cfala#u0, r5f100cgala#u0 r5f100caala#w0, r5f100ccala#w0, r5f100cdala#w0, r5f100ceala#w0, r5f100cfala#w0, r5f100cgala#w0 r5f100cagla#u0, r5f100ccgla#u0, r5f100cdgla#u0, r5f100cegla#u0, r5f100cfgla#u0, r5f100cggla#u0 r5f100cagla#w0, r5f100ccgla#w0, r5f100cdgla#w0, r5f100cegla#w0, r5f100cfgla#w0, r5f100cggla#w0 36 pins 36-pin plastic wflga (4 ? 4 mm, 0.5 mm pitch) not mounted a r5f101caala#u0, r5f101ccala#u0, r5f101cdala#u0, r5f101ceala#u0, r5f101cfala#u0, r5f101cgala#u0 r5f101caala#w0, r5f101ccala#w0, r5f101cdala#w0, r5f101ceala#w0, r5f101cfala#w0, r5f101cgala#w0 mounted a d g r5f100eaana#u0, r5f100ecana#u0, r5f100edana#u0, r5f100eeana#u0, r5f100efana#u0, r5f100egana#u0, r5f100ehana#u0 r5f100eaana#w0, r5f100ecana#w0, r5f100edana#w0, r5f100eeana#w0, r5f100efana#w0, r5f100egana#w0, r5f100ehana#w0 r5f100eadna#u0, r5f100ecdna#u0, r5f100eddna#u0, r5f100eedna#u0, r5f100efdna#u0, r5f100egdna#u0, r5f100ehdna#u0 r5f100eadna#w0, r5f100ecdna#w0, r5f100eddna#w0, r5f100eedna#w0, r5f100efdna#w0, r5f100egdna#w0, r5f100ehdna#w0 r5f100eagna#u0, r5f100ecgna#u0, r5f100edgna#u0, r5f100eegna#u0, r5f100efgna#u0, r5f100eggna#u0, r5f100ehgna#u0 r5f100eagna#w0, r5f100ecgna#w0, r5f100edgna#w0, r5f100eegna#w0, r5f100efgna#w0, r5f100eggna#w0, r5f100ehgna#w0 40 pins 40-pin plastic hwqfn (6 ? 6 mm, 0.5 mm pitch) not mounted a d r5f101eaana#u0, r5f101ecana#u0, r5f101edana#u0, r5f101eeana#u0, r5f101efana#u0, r5f101egana#u0, r5f101ehana#u0 r5f101eaana#w0, r5f101ecana#w0, r5f101edana#w0, r5f101eeana#w0, r5f101efana#w0, r5f101egana#w0, r5f101ehana#w0 r5f101eadna#u0, r5f101ecdna#u0, r5f101eddna#u0, r5f101eedna#u0, r5f101efdna#u0, r5f101egdna#u0, r5f101ehdna#u0 r5f101eadna#w0, r5f101ecdna#w0, r5f101eddna#w0, r5f101eedna#w0, r5f101efdna#w0, r5f101egdna#w0, r5f101ehdna#w0 note for the fields of application, refer to figure 1-1 part number, memory size, and package of rl78/g13 . caution the ordering part numbers represent the numbers at the time of publication. for the latest ordering part numbers, refer to the target product page of the renesas electronics website.
rl78/g13 1. outline page 7 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 table 1-1. list of ordering part numbers (4/12) pin count package data flash fields of application note ordering part number mounted a d g r5f100faafp#v0, r5f100fcafp#v0, r5f100fdafp#v0, r5f100feafp#v0, r5f100ffafp#v0, r5f100fgafp#v0, r5f100fhafp#v0, r5f100fjafp#v0, r5f100fkafp#v0, r5f100flafp#v0 r5f100faafp#x0, r5f100fcafp#x0, r5f100fdafp#x0, r5f100feafp#x0, r5f100ffafp#x0, r5f100fgafp#x0, r5f100fhafp#x0, r5f100fjafp#x0, r5f100fkafp#x0, r5f100flafp#x0 r5f100fadfp#v0, r5f100fcdfp#v0, r5f100fddfp#v0, r5f100fedfp#v0, r5f100ffdfp#v0, r5f100fgdfp#v0, r5f100fhdfp#v0, r5f100fjdfp#v0, r5f100fkdfp#v0, r5f100fldfp#v0 r5f100fadfp#x0, r5f100fcdfp#x0, r5f100fddfp#x0, r5f100fedfp#x0, r5f100ffdfp#x0, r5f100fgdfp#x0, r5f100fhdfp#x0, r5f100fjdfp#x0, r5f100fkdfp#x0, r5f100fldfp#x0 r5f100fagfp#v0, r5f100fcgfp#v0, r5f100fdgfp#v0, r5f100fegfp#v0, r5f100ffgfp#v0, r5f100fggfp#v0, r5f100fhgfp#v0, r5f100fjgfp#v0 r5f100fagfp#x0, r5f100fcgfp#x0, r5f100fdgfp#x0, r5f100fegfp#x0, r5f100ffgfp#x0, r5f100fggfp#x0, r5f100fhgfp#x0, r5f100fjgfp#x0 44 pins 44-pin plastic lqfp (10 ? 10 mm, 0.8 mm pitch) not mounted a d r5f101faafp#v0, r5f101fcafp#v0, r5f101fdafp#v0, r5f101feafp#v0, r5f101ffafp#v0, r5f101fgafp#v0, r5f101fhafp#v0, r5f101fjafp#v0, r5f101fkafp#v0, r5f101flafp#v0 r5f101faafp#x0, r5f101fcafp#x0, r5f101fdafp#x0, r5f101feafp#x0, r5f101ffafp#x0, r5f101fgafp#x0, r5f101fhafp#x0, r5f101fjafp#x0, r5f101fkafp#x0, r5f101flafp#x0 r5f101fadfp#v0, r5f101fcdfp#v0, r5f101fddfp#v0, r5f101fedfp#v0, r5f101ffdfp#v0, r5f101fgdfp#v0, r5f101fhdfp#v0, r5f101fjdfp#v0, r5f101fkdfp#v0, r5f101fldfp#v0 r5f101fadfp#x0, r5f101fcdfp#x0, r5f101fddfp#x0, r5f101fedfp#x0, r5f101ffdfp#x0, r5f101fgdfp#x0, r5f101fhdfp#x0, r5f101fjdfp#x0, r5f101fkdfp#x0, r5f101fldfp#x0 note for the fields of application, refer to figure 1-1 part number, memory size, and package of rl78/g13 . caution the ordering part numbers represent the numbers at the time of publication. for the latest ordering part numbers, refer to the target product page of the renesas electronics website.
rl78/g13 1. outline page 8 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 table 1-1. list of ordering part numbers (5/12) pin count package data flash fields of application note ordering part number mounted a d g r5f100gaafb#v0, r5f100gcafb#v0, r5f100gdafb#v0, r5f100geafb#v0, r5f100gfafb#v0, r5f100ggafb#v0, r5f100ghafb#v0, r5f100gjafb#v0, r5f100gkafb#v0, r5f100glafb#v0 r5f100gaafb#x0, r5f100gcafb#x0, r5f100gdafb#x0, r5f100geafb#x0, r5f100gfafb#x0, r5f100ggafb#x0, r5f100ghafb#x0, r5f100gjafb#x0, r5f100gkafb#x0, r5f100glafb#x0 r5f100gadfb#v0, r5f100g cdfb#v0, r5f100gddfb#v0, r5f100gedfb#v0, r5f100gfdfb#v0, r5f100ggdfb#v0, r5f100ghdfb#v0, r5f100gjdfb#v0, r5f100gkdfb#v0, r5f100gldfb#v0 r5f100gadfb#x0, r5f100g cdfb#x0, r5f100gddfb#x0, r5f100gedfb#x0, r5f100gfdfb#x0, r5f100ggdfb#x0, r5f100ghdfb#x0, r5f100gjdfb#x0, r5f100gkdfb#x0, r5f100gldfb#x0 r5f100gagfb#v0, r5f100gcgfb#v0, r5f100gdgfb#v0, r5f100gegfb#v0, r5f100gfgfb#v0, r5f100gggfb#v0, r5f100ghgfb#v0, r5f100gjgfb#v0 r5f100gagfb#x0, r5f100gcgfb#x0, r5f100gdgfb#x0, r5f100gegfb#x0, r5f100gfgfb#x0, r5f100gggfb#x0, r5f100ghgfb#x0, r5f100gjgfb#x0 48 pins 48-pin plastic lfqfp (7 ? 7 mm, 0.5 mm pitch) not mounted a d r5f101gaafb#v0, r5f101gcafb#v0, r5f101gdafb#v0, r5f101geafb#v0, r5f101gfafb#v0, r5f101ggafb#v0, r5f101ghafb#v0, r5f101gjafb#v0, r5f101gkafb#v0, r5f101glafb#v0 r5f101gaafb#x0, r5f101gcafb#x0, r5f101gdafb#x0, r5f101geafb#x0, r5f101gfafb#x0, r5f101ggafb#x0, r5f101ghafb#x0, r5f101gjafb#x0, r5f101gkafb#x0, r5f101glafb#x0 r5f101gadfb#v0, r5f101g cdfb#v0, r5f101gddfb#v0, r5f101gedfb#v0, r5f101gfdfb#v0, r5f101ggdfb#v0, r5f101ghdfb#v0, r5f101gjdfb#v0, r5f101gkdfb#v0, r5f101gldfb#v0 r5f101gadfb#x0, r5f101g cdfb#x0, r5f101gddfb#x0, r5f101gedfb#x0, r5f101gfdfb#x0, r5f101ggdfb#x0, r5f101ghdfb#x0, r5f101gjdfb#x0, r5f101gkdfb#x0, r5f101gldfb#x0 note for the fields of application, refer to figure 1-1 part number, memory size, and package of rl78/g13 . caution the ordering part numbers represent the numbers at the time of publication. for the latest ordering part numbers, refer to the target product page of the renesas electronics website.
rl78/g13 1. outline page 9 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 table 1-1. list of ordering part numbers (6/12) pin count package data flash fields of application note ordering part number mounted a d g r5f100gaana#u0, r5f100gcana#u0, r5f100gdana#u0, r5f100geana#u0, r5f100gfana#u0, r5f100ggana#u0, r5f100ghana#u0, r5f100gjana#u0, r5f100gkana#u0, r5f100glana#u0 r5f100gaana#w0, r5f100gcana#w0, r5f100gdana#w0, r5f100geana#w0, r5f100gfana#w0, r5f100ggana#w0, r5f100ghana#w0, r5f100gjana#w0, r5f100gkana#w0, r5f100glana#w0 r5f100gadna#u0, r5f100gcdna#u0, r5f100gddna#u0, r5f100gedna#u0, r5f100gfdna#u0, r5f100ggdna#u0, r5f100ghdna#u0, r5f100gjdna#u0, r5f100gkdna#u0, r5f100gldna#u0 r5f100gadna#w0, r5f100gcdna#w0, r5f100gddna#w0, r5f100gedna#w0, r5f100gfdna#w0, r5f100ggdna#w0, r5f100ghdna#w0, r5f100gjdna#w0, r5f100gkdna#w0, r5f100gldna#w0 r5f100gagna#u0, r5f100gcgna#u0, r5f100gdgna#u0, r5f100gegna#u0, r5f100gfgna#u0, r5f100gggna#u0, r5f100ghgna#u0, r5f100gjgna#u0 r5f100gagna#w0, r5f100gcgna#w0, r5f100gdgna#w0, r5f100gegna#w0, r5f100gfgna#w0, r5f100gggna#w0, r5f100ghgna#w0, r5f100gjgna#w0 48 pins 48-pin plastic hwqfn (7 ? 7 mm, 0.5 mm pitch) not mounted a d r5f101gaana#u0, r5f101gcana#u0, r5f101gdana#u0, r5f101geana#u0, r5f101gfana#u0, r5f101ggana#u0, r5f101ghana#u0, r5f101gjana#u0, r5f101gkana#u0, r5f101glana#u0 r5f101gaana#w0, r5f101gcana#w0, r5f101gdana#w0, r5f101geana#w0, r5f101gfana#w0, r5f101ggana#w0, r5f101ghana#w0, r5f101gjana#w0, r5f101gkana#w0, r5f101glana#w0 r5f101gadna#u0, r5f101gcdna#u0, r5f101gddna#u0, r5f101gedna#u0, r5f101gfdna#u0, r5f101ggdna#u0, r5f101ghdna#u0, r5f101gjdna#u0, r5f101gkdna#u0, r5f101gldna#u0 r5f101gadna#w0, r5f101gcdna#w0, r5f101gddna#w0, r5f101gedna#w0, r5f101gfdna#w0, r5f101ggdna#w0, r5f101ghdna#w0, r5f101gjdna#w0, r5f101gkdna#w0, r5f101gldna#w0 note for the fields of application, refer to figure 1-1 part number, memory size, and package of rl78/g13 . caution the ordering part numbers represent the numbers at the time of publication. for the latest ordering part numbers, refer to the target product page of the renesas electronics website.
rl78/g13 1. outline page 10 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 table 1-1. list of ordering part numbers (7/12) pin count package data flash fields of application note ordering part number mounted a d g r5f100jcafa#v0, r5f100jdafa#v0, r5f100jeafa#v0, r5f100jfafa#v0, r5f100jgafa#v0, r5f100jhafa#v0, r5f100jjafa#v0, r5f100jkafa#v0, r5f100jlafa#v0 r5f100jcafa#x0, r5f100jdafa#x0, r5f100jeafa#x0, r5f100jfafa#x0, r5f100jgafa#x0, r5f100jhafa#x0, r5f100jjafa#x0, r5f100jkafa#x0, r5f100jlafa#x0 r5f100jcdfa#v0, r5f100jddfa#v0, r5f100jedfa#v0, r5f100jfdfa#v0, r5f100jgdfa#v0, r5f100jhdfa#v0, r5f100jjdfa#v0, r5f100jkdfa#v0, r5f100jldfa#v0 r5f100jcdfa#x0, r5f100jddfa#x0, r5f100jedfa#x0, r5f100jfdfa#x0, r5f100jgdfa#x0, r5f100jhdfa#x0, r5f100jjdfa#x0, r5f100jkdfa#x0, r5f100jldfa#x0 r5f100jcgfa#v0, r5f100jdgfa#v0, r5f100jegfa#v0, r5f100jfgfa#v0,r5f100jggfa#v0, r5f100jhgfa#v0, r5f100jjgfa#v0 r5f100jcgfa#x0, r5f100jdgfa#x0, r5f100jegfa#x0, r5f100jfgfa#x0,r5f100jggfa#x0, r5f100jhgfa#x0, r5f100jjgfa#x0 52 pins 52-pin plastic lqfp (10 ? 10 mm, 0.65 mm pitch) not mounted a d r5f101jcafa#v0, r5f101jdafa#v0, r5f101jeafa#v0, r5f101jfafa#v0, r5f101jgafa#v0, r5f101jhafa#v0, r5f101jjafa#v0, r5f101jkafa#v0, r5f101jlafa#v0 r5f101jcafa#x0, r5f101jdafa#x0, r5f101jeafa#x0, r5f101jfafa#x0, r5f101jgafa#x0, r5f101jhafa#x0, r5f101jjafa#x0, r5f101jkafa#x0, r5f101jlafa#x0 r5f101jcdfa#v0, r5f101jddfa#v0, r5f101jedfa#v0, r5f101jfdfa#v0, r5f101jgdfa#v0, r5f101jhdfa#v0, r5f101jjdfa#v0, r5f101jkdfa#v0, r5f101jldfa#v0 r5f101jcdfa#x0, r5f101jddfa#x0, r5f101jedfa#x0, r5f101jfdfa#x0, r5f101jgdfa#x0, r5f101jhdfa#x0, r5f101jjdfa#x0, r5f101jkdfa#x0, r5f101jldfa#x0 note for the fields of application, refer to figure 1-1 part number, memory size, and package of rl78/g13 . caution the ordering part numbers represent the numbers at the time of publication. for the latest ordering part numbers, refer to the target product page of the renesas electronics website.
rl78/g13 1. outline page 11 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 table 1-1. list of ordering part numbers (8/12) pin count package data flash fields of application note ordering part number mounted a d g r5f100lcafa#v0, r5f100ldafa#v0, r5f100leafa#v0, r5f100lfafa#v0, r5f100lgafa#v0, r5f100lhafa#v0, r5f100ljafa#v0, r5f100lkafa#v0, r5f100llafa#v0 r5f100lcafa#x0, r5f100ldafa#x0, r5f100leafa#x0, r5f100lfafa#x0, r5f100lgafa#x0, r5f100lhafa#x0, r5f100ljafa#x0, r5f100lkafa#x0, r5f100llafa#x0 r5f100lcdfa#v0, r5f100lddfa#v0, r5f100ledfa#v0, r5f100lfdfa#v0, r5f100lgdfa#v0, r5f100lhdfa#v0, r5f100ljdfa#v0, r5f100lkdfa#v0, r5f100lldfa#v0 r5f100lcdfa#x0, r5f100lddfa#x0, r5f100ledfa#x0, r5f100lfdfa#x0, r5f100lgdfa#x0, r5f100lhdfa#x0, r5f100ljdfa#x0, r5f100lkdfa#x0, r5f100lldfa#x0 r5f100lcgfa#v0, r5f100ldgfa#v0, r5f100legfa#v0, r5f100lfgfa#v0 r5f100lcgfa#x0, r5f100ldgfa#x0, r5f100legfa#x0, r5f100lfgfa#x0 r5f100lggfa#v0, r5f100lhgfa#v0, r5f100ljgfa#v0 r5f100lggfa#x0, r5f100lhgfa#x0, r5f100ljgfa#x0 64 pins 64-pin plastic lqfp (12 ? 12 mm, 0.65 mm pitch) not mounted a d r5f101lcafa#v0, r5f101ldafa#v0, r5f101leafa#v0, r5f101lfafa#v0, r5f101lgafa#v0, r5f101lhafa#v0, r5f101ljafa#v0, r5f101lkafa#v0, r5f101llafa#v0 r5f101lcafa#x0, r5f101ldafa#x0, r5f101leafa#x0, r5f101lfafa#x0, r5f101lgafa#x0, r5f101lhafa#x0, r5f101ljafa#x0, r5f101lkafa#x0, r5f101llafa#x0 r5f101lcdfa#v0, r5f101lddfa#v0, r5f101ledfa#v0, r5f101lfdfa#v0, r5f101lgdfa#v0, r5f101lhdfa#v0, r5f101ljdfa#v0, r5f101lkdfa#v0, r5f101lldfa#v0 r5f101lcdfa#x0, r5f101lddfa#x0, r5f101ledfa#x0, r5f101lfdfa#x0, r5f101lgdfa#x0, r5f101lhdfa#x0, r5f101ljdfa#x0, r5f101lkdfa#x0, r5f101lldfa#x0 note for the fields of application, refer to figure 1-1 part number, memory size, and package of rl78/g13 . caution the ordering part numbers represent the numbers at the time of publication. for the latest ordering part numbers, refer to the target product page of the renesas electronics website.
rl78/g13 1. outline page 12 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 table 1-1. list of ordering part numbers (9/12) pin count package data flash fields of application note ordering part number mounted a d g r5f100lcafb#v0, r5f100ldafb#v0, r5f100leafb#v0, r5f100lfafb#v0, r5f100lgafb#v0, r5f100lhafb#v0, r5f100ljafb#v0, r5f100lkafb#v0, r5f100llafb#v0 r5f100lcafb#x0, r5f100ldafb#x0, r5f100leafb#x0, r5f100lfafb#x0, r5f100lgafb#x0, r5f100lhafb#x0, r5f100ljafb#x0, r5f100lkafb#x0, r5f100llafb#x0 r5f100lcdfb#v0, r5f100lddfb#v0, r5f100ledfb#v0, r5f100lfdfb#v0, r5f100lgdfb#v0, r5f100lhdfb#v0, r5f100ljdfb#v0, r5f100lkdfb#v0, r5f100lldfb#v0 r5f100lcdfb#x0, r5f100lddfb#x0, r5f100ledfb#x0, r5f100lfdfb#x0, r5f100lgdfb#x0, r5f100lhdfb#x0, r5f100ljdfb#x0, r5f100lkdfb#x0, r5f100lldfb#x0 r5f100lcgfb#v0, r5f100ldgfb#v0, r5f100legfb#v0, r5f100lfgfb#v0 r5f100lcgfb#x0, r5f100ldgfb#x0, r5f100legfb#x0, r5f100lfgfb#x0 r5f100lggfb#v0, r5f100lhgfb#v0, r5f100ljgfb#v0 r5f100lggfb#x0, r5f100lhgfb#x0, r5f100ljgfb#x0 64-pin plastic lfqfp (10 ? 10 mm, 0.5 mm pitch) not mounted a d r5f101lcafb#v0, r5f101ldafb#v0, r5f101leafb#v0, r5f101lfafb#v0, r5f101lgafb#v0, r5f101lhafb#v0, r5f101ljafb#v0, r5f101lkafb#v0, r5f101llafb#v0 r5f101lcafb#x0, r5f101ldafb#x0, r5f101leafb#x0, r5f101lfafb#x0, r5f101lgafb#x0, r5f101lhafb#x0, r5f101ljafb#x0, r5f101lkafb#x0, r5f101llafb#x0 r5f101lcdfb#v0, r5f101lddfb#v0, r5f101ledfb#v0, r5f101lfdfb#v0, r5f101lgdfb#v0, r5f101lhdfb#v0, r5f101ljdfb#v0, r5f101lkdfb#v0, r5f101lldfb#v0 r5f101lcdfb#x0, r5f101lddfb#x0, r5f101ledfb#x0, r5f101lfdfb#x0, r5f101lgdfb#x0, r5f101lhdfb#x0, r5f101ljdfb#x0, r5f101lkdfb#x0, r5f101lldfb#x0 mounted a g r5f100lcabg#u0, r5f100ldabg#u0, r5f100leabg#u0, r5f100lfabg#u0, r5f100lgabg#u0, r5f100lhabg#u0, r5f100ljabg#u0 r5f100lcabg#w0, r5f100ldabg#w0, r5f100leabg#w0, r5f100lfabg#w0, r5f100lgabg#w0, r5f100lhabg#w0, r5f100ljabg#w0 r5f100lcgbg#u0, r5f100ldgbg#u0, r5f100legbg#u0, r5f100lfgbg#u0, r5f100lggbg#u0, r5f100lhgbg#u0, r5f100ljgbg#u0 r5f100lcgbg#w0, r5f100ldgbg#w0, r5f100legbg#w0, r5f100lfgbg#w0, r5f100lggbg#w0, r5f100lhgbg#w0, r5f100ljgbg#w0 64 pins 64-pin plastic vfbga (4 ? 4 mm, 0.4 mm pitch) not mounted a r5f101lcabg#u0, r5f101ldabg#u0, r5f101leabg#u0, r5f101lfabg#u0, r5f101lgabg#u0, r5f101lhabg#u0, r5f101ljabg#u0 r5f101lcabg#w0, r5f101ldabg#w0, r5f101leabg#w0, r5f101lfabg#w0, r5f101lgabg#w0, r5f101lhabg#w0, r5f101ljabg#w0 note for the fields of application, refer to figure 1-1 part number, memory size, and package of rl78/g13 . caution the ordering part numbers represent the numbers at the time of publication. for the latest ordering part numbers, refer to the target product page of the renesas electronics website.
rl78/g13 1. outline page 13 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 table 1-1. list of ordering part numbers (10/12) pin count package data flash fields of application note ordering part number mounted a d g r5f100mfafa#v0, r5f100mgafa#v0, r5f100mhafa#v0, r5f100mjafa#v0, r5f100mkafa#v0, r5f100mlafa#v0 r5f100mfafa#x0, r5f100mgafa#x0, r5f100mhafa#x0, r5f100mjafa#x0, r5f100mkafa#x0, r5f100mlafa#x0 r5f100mfdfa#v0, r5f100mgdfa#v0, r5f100mhdfa#v0, r5f100mjdfa#v0, r5f100mkdfa#v0, r5f100mldfa#v0 r5f100mfdfa#x0, r5f100mgdfa#x0, r5f100mhdfa#x0, r5f100mjdfa#x0, r5f100mkdfa#x0, r5f100mldfa#x0 r5f100mfgfa#v0, r5f100mggfa#v0, r5f100mhgfa#v0, r5f100mjgfa#v0 r5f100mfgfa#x0, r5f100mggfa#x0, r5f100mhgfa#x0, r5f100mjgfa#x0 80-pin plastic lqfp (14 ? 14 mm, 0.65 mm pitch) not mounted a d r5f101mfafa#v0, r5f101mgafa#v0, r5f101mhafa#v0, r5f101mjafa#v0, r5f101mkafa#v0, r5f101mlafa#v0 r5f101mfafa#x0, r5f101mgafa#x0, r5f101mhafa#x0, r5f101mjafa#x0, r5f101mkafa#x0, r5f101mlafa#x0 r5f101mfdfa#v0, r5f101mgdfa#v0, r5f101mhdfa#v0, r5f101mjdfa#v0, r5f101mkdfa#v0, r5f101mldfa#v0 r5f101mfdfa#x0, r5f101mgdfa#x0, r5f101mhdfa#x0, r5f101mjdfa#x0, r5f101mkdfa#x0, r5f101mldfa#x0 mounted a d g r5f100mfafb#v0, r5f100mgafb#v0, r5f100mhafb#v0, r5f100mjafb#v0, r5f100mkafb#v0, r5f100mlafb#v0 r5f100mfafb#x0, r5f100mgafb#x0, r5f100mhafb#x0, r5f100mjafb#x0, r5f100mkafb#x0, r5f100mlafb#x0 r5f100mfdfb#v0, r5f100mgdfb#v0, r5f100mhdfb#v0, r5f100mjdfb#v0, r5f100mkdfb#v0, r5f100mldfb#v0 r5f100mfdfb#x0, r5f100mgdfb#x0, r5f100mhdfb#x0, r5f100mjdfb#x0, r5f100mkdfb#x0, r5f100mldfb#x0 r5f100mfgfb#v0, r5f100mggfb#v0, r5f100mhgfb#v0, r5f100mjgfb#v0 r5f100mfgfb#x0, r5f100mggfb#x0, r5f100mhgfb#x0, r5f100mjgfb#x0 80 pins 80-pin plastic lfqfp (12 ? 12 mm, 0.5 mm pitch) not mounted a d r5f101mfafb#v0, r5f101mgafb#v0, r5f101mhafb#v0, r5f101mjafb#v0, r5f101mkafb#v0, r5f101mlafb#v0 r5f101mfafb#x0, r5f101mgafb#x0, r5f101mhafb#x0, r5f101mjafb#x0, r5f101mkafb#x0, r5f101mlafb#x0 r5f101mfdfb#v0, r5f101mgdfb#v0, r5f101mhdfb#v0, r5f101mjdfb#v0, r5f101mkdfb#v0, r5f101mldfb#v0 r5f101mfdfb#x0, r5f101mgdfb#x0, r5f101mhdfb#x0, r5f101mjdfb#x0, r5f101mkdfb#x0, r5f101mldfb#x0 note for the fields of application, refer to figure 1-1 part number, memory size, and package of rl78/g13 . caution the ordering part numbers represent the numbers at the time of publication. for the latest ordering part numbers, refer to the target product page of the renesas electronics website.
rl78/g13 1. outline page 14 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 table 1-1. list of ordering part numbers (11/12) pin count package data flash fields of application note ordering part number mounted a d g r5f100pfafb#v0, r5f100pgafb#v0, r5f100phafb#v0, r5f100pjafb#v0, r5f100pkafb#v0, r5f100plafb#v0 r5f100pfafb#x0, r5f100pgafb#x0, r5f100phafb#x0, r5f100pjafb#x0, r5f100pkafb#x0, r5f100plafb#x0 r5f100pfdfb#v0, r5f100pgdfb#v0, r5f100phdfb#v0, r5f100pjdfb#v0, r5f100pkdfb#v0, r5f100pldfb#v0 r5f100pfdfb#x0, r5f100pgdfb#x0, r5f100phdfb#x0, r5f100pjdfb#x0, r5f100pkdfb#x0, r5f100pldfb#x0 r5f100pfgfb#v0, r5f100pggfb#v0, r5f100phgfb#v0, r5f100pjgfb#v0 r5f100pfgfb#x0, r5f100pggfb#x0, r5f100phgfb#x0, r5f100pjgfb#x0 100-pin plastic lfqfp (14 ? 14 mm, 0.5 mm pitch) not mounted a d r5f101pfafb#v0, r5f101pgafb#v0, r5f101phafb#v0, r5f101pjafb#v0, r5f101pkafb#v0, r5f101plafb#v0 r5f101pfafb#x0, r5f101pgafb#x0, r5f101phafb#x0, r5f101pjafb#x0, r5f101pkafb#x0, r5f101plafb#x0 r5f101pfdfb#v0, r5f101pgdfb#v0, r5f101phdfb#v0, r5f101pjdfb#v0, r5f101pkdfb#v0, r5f101pldfb#v0 r5f101pfdfb#x0, r5f101pgdfb#x0, r5f101phdfb#x0, r5f101pjdfb#x0, r5f101pkdfb#x0, r5f101pldfb#x0 mounted a d g r5f100pfafa#v0, r5f100pgafa#v0, r5f100phafa#v0, r5f100pjafa#v0, r5f100pkafa#v0, r5f100plafa#v0 r5f100pfafa#x0, r5f100pgafa#x0, r5f100phafa#x0, r5f100pjafa#x0, r5f100pkafa#x0, r5f100plafa#x0 r5f100pfdfa#v0, r5f100pgdfa#v0, r5f100phdfa#v0, r5f100pjdfa#v0, r5f100pkdfa#v0, r5f100pldfa#v0 r5f100pfdfa#x0, r5f100pgdfa#x0, r5f100phdfa#x0, r5f100pjdfa#x0, r5f100pkdfa#x0, r5f100pldfa#x0 r5f100pfgfa#v0, r5f100pggfa#v0, r5f100phgfa#v0, r5f100pjgfa#v0 r5f100pfgfa#x0, r5f100pggfa#x0, r5f100phgfa#x0, r5f100pjgfa#x0 100 pins 100-pin plastic lqfp (14 ? 20 mm, 0.65 mm pitch) not mounted a d r5f101pfafa#v0, r5f101pgafa#v0, r5f101phafa#v0, r5f101pjafa#v0, r5f101pkafa#v0, r5f101plafa#v0 r5f101pfafa#x0, r5f101pgafa#x0, r5f101phafa#x0, r5f101pjafa#x0, r5f101pkafa#x0, r5f101plafa#x0 r5f101pfdfa#v0, r5f101pgdfa#v0, r5f101phdfa#v0, r5f101pjdfa#v0, r5f101pkdfa#v0, r5f101pldfa#v0 r5f101pfdfa#x0, r5f101pgdfa#x0, r5f101phdfa#x0, r5f101pjdfa#x0, r5f101pkdfa#x0, r5f101pldfa#x0 note for the fields of application, refer to figure 1-1 part number, memory size, and package of rl78/g13 . caution the ordering part numbers represent the numbers at the time of publication. for the latest ordering part numbers, refer to the target product page of the renesas electronics website.
rl78/g13 1. outline page 15 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 table 1-1. list of ordering part numbers (12/12) pin count package data flash fields of application note ordering part number mounted a d r5f100shafb#v0, r5f100sjafb#v0, r5f100skafb#v0, r5f100slafb#v0 r5f100shafb#x0, r5f100sjafb#x0, r5f100skafb#x0, r5f100slafb#x0 r5f100shdfb#v0, r5f100sjdfb#v0, r5f100skdfb#v0, r5f100sldfb#v0 r5f100shdfb#x0, r5f100sjdfb#x0, r5f100skdfb#x0, r5f100sldfb#x0 128 pins 128-pin plastic lfqfp (14 ? 20 mm, 0.5 mm pitch) not mounted a d r5f101shafb#v0, r5f101sjafb#v0, r5f101skafb#v0, r5f101slafb#v0 r5f101shafb#x0, r5f101sjafb#x0, r5f101skafb#x0, r5f101slafb#x0 r5f101shdfb#v0, r5f101sjdfb#v0, r5f101skdfb#v0, r5f101sldfb#v0 r5f101shdfb#x0, r5f101sjdfb#x0, r5f101skdfb#x0, r5f101sldfb#x0 note for the fields of application, refer to figure 1-1 part number, memory size, and package of rl78/g13 . caution the ordering part numbers represent the numbers at the time of publication. for the latest ordering part numbers, refer to the target product page of the renesas electronics website.
rl78/g13 1. outline page 16 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.3 pin configuration (top view) 1.3.1 20-pin products ? 20-pin plastic lssop (7.62 mm (300), 0.65 mm pitch) 20 19 18 17 16 15 14 13 12 11 rl78/g13 (top view) 1 2 3 4 5 6 7 8 9 10 p20/ani0/av refp p21/ani1/av refm p22/ani2 p147/ani18 p10/sck00/scl00 p11/si00/rxd0/toolrxd/sda00 p12/so00/txd0/tooltxd p16/ti01/to01/intp5/so11 p17/ti02/to02/si11/sda11 p30/intp3/sck11/scl11 p01/ani16/to00/rxd1 p00/ani17/ti00/txd1 p40/tool0 reset p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd caution connect the regc pin to vss via a capacitor (0.47 to 1 ? f). remark for pin identification, see 1.4 pin identification .
rl78/g13 1. outline page 17 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.3.2 24-pin products ? 24-pin plastic hwqfn (4 4 mm, 0.5 mm pitch) 12 11 10 9 8 7 19 20 21 22 23 24 18 17 16 15 14 13 1 2 3 4 5 6 p21/ani1/av refm p20/ani0/av refp p01/ani16/to00/rxd1 p00/ani17/ti00/txd1 p40/tool0 reset exposed die pad rl78/g13 (top view) p22/ani2 p147/ani18 p10/sck00/scl00 p11/si00/rxd0/toolrxd/sda00 p12/so00/txd0/tooltxd p16/ti01/to01/intp5 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p17/ti02/to02/so11 p50/intp1/si11/sda11 p30/intp3/sck11/scl11 p31/ti03/to03/intp4/pclbuz0 p61/sdaa0 p60/scla0 index mark caution connect the regc pin to vss via a capacitor (0.47 to 1 ? f). remarks 1. for pin identification, see 1.4 pin identification . 2. it is recommended to connect an exposed die pad to v ss .
rl78/g13 1. outline page 18 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.3.3 25-pin products ? 25-pin plastic wflga (3 3 mm, 0.50 mm pitch) index mark top view rl78/g13 (top view) bottom view 5 4 3 2 1 abcde edcba index mark a b c d e 5 p40/tool0 reset p01/ani16/ to00/rxd1 p22/ani2 p147/ani18 5 4 p122/x2/ exclk p137/intp0 p00/ani17/ ti00/txd1 p21/ani1/ av refm p10/sck00/ scl00 4 3 p121/x1 v dd p20/ani0/ av refp p12/so00/ txd0/ tooltxd p11/si00/ rxd0/ toolrxd/ sda00 3 2 regc v ss p30/intp3/ sck11/scl11 p17/ti02/ to02/so11 p50/intp1/ si11/sda11 2 1 p60/scla0 p61/sdaa0 p31/ti03/ to03/intp4/ pclbuz0 p16/ti01/ to01/intp5 p130 1 a b c d e caution connect the regc pin to vss via a capacitor (0.47 to 1 ? f). remark for pin identification, see 1.4 pin identification .
rl78/g13 1. outline page 19 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.3.4 30-pin products ? 30-pin plastic lssop (7.62 mm (300), 0.65 mm pitch) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 p21/ani1/av refm p22/ani2 p23/ani3 p147/ani18 p10/sck00/s cl00/(ti07)/(to07) p11/s i00/rxd0/toolrxd/s da00/(ti06)/(to06) p12/s o00/txd0/tooltxd/(ti05)/(to05) p13/txd2/so20/(s daa0)/(ti04)/(to04) p14/rxd2/si20/s da20/(scla0)/(ti03 )/(to03) p15/pclbuz1/ sck20/s cl20/(ti02)/(to02) p16/ti01/to01/intp5/(rxd0) p17/ti02/to02/(txd0) p51/intp2/so11 p50/intp1/si11/s da11 p30/intp3/sck11/scl11 p20/ani0/av refp p01/ani16/to00/rxd1 p00/ani17/ti00/txd1 p120/ani19 p40/tool0 reset p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p60/scla0 p61/s daa0 p31/ti03 /to03 /intp4/pclbuz0 rl78/g13 (top view) caution connect the regc pin to vss via a capacitor (0.47 to 1 ? f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via setting s in the peripheral i/o redirection register (pior). refer to figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 20 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.3.5 32-pin products ? 32-pin plastic hwqfn (5 5 mm, 0.5 mm pitch) 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 p147/ani18 p23/ani3 p22/ani2 p21/ani1/av refm p20/ani0/av refp p01/ani16/to00/rxd1 p00/ani17/ti00/txd1 p120/ani19 p51/intp2/so11 p50/intp1/si11/sda11 p30/intp3/sck11/scl11 p70 p31/ti03/to03/intp4/pclbuz0 p62 p61/sdaa0 p60/scla0 exposed die pad rl78/g13 (top view) p10/sck00/scl00/(ti07)/(to07) p11/si00/rxd0/toolrxd/sda00/(ti06)/(to06) p12/so00/txd0/tooltxd/(ti05)/(to05) p13/txd2/so20/(sdaa0)/(ti04)/(to04) p14/rxd2/si20/sda20/(scla0)/(ti03)/(to03) p15/pclbuz1/sck20/scl20/(ti02)/(to02) p16/ti01/to01/intp5/(rxd0) p17/ti02/to02/(txd0) p40/tool0 reset p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd index mark caution connect the regc pin to vss via a capacitor (0.47 to 1 ? f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via setting s in the peripheral i/o redirection register (pior). refer to figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g13 user?s manual. 3. it is recommended to connect an exposed die pad to v ss .
rl78/g13 1. outline page 21 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.3.6 36-pin products ? 36-pin plastic wflga (4 4 mm, 0.5 mm pitch) top view rl78/g13 (top view) bottom view fedcba abcdef 6 5 4 3 2 1 index mark a b c d e f 6 p60/scla0 v dd p121/x1 p122/x2/exclk p137/intp0 p40/tool0 6 5 p62 p61/sdaa0 v ss regc reset p120/ani19 5 4 p72/so21 p71/si21/ sda21 p14/rxd2/si20/ sda20/(scla0) /(ti03)/(to03) p31/ti03/to03/ intp4/ pclbuz0 p00/ti00/txd1 p01/to00/rxd1 4 3 p50/intp1/ si11/sda11 p70/sck21/ scl21 p15/pclbuz1/ sck20/scl20/ (ti02)/(to02) p22/ani2 p20/ani0/ av refp p21/ani1/ av refm 3 2 p30/intp3/ sck11/scl11 p16/ti01/to01/ intp5/(rxd0) p12/so00/ txd0/tooltxd /(ti05)/(to05) p11/si00/rxd0/ toolrxd/ sda00/(ti06)/ (to06) p24/ani4 p23/ani3 2 1 p51/intp2/ so11 p17/ti02/to02/ (txd0) p13/txd2/ so20/(sdaa0)/ (ti04)/(to04) p10/sck00/ scl00/(ti07)/ (to07) p147/ani18 p25/ani5 1 a b c d e f caution connect the regc pin to vss via a capacitor (0.47 to 1 ? f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via setting s in the peripheral i/o redirection register (pior). refer to figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 22 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.3.7 40-pin products ? 40-pin plastic hwqfn (6 6 mm, 0.5 mm pitch) 20 19 18 17 16 15 14 13 12 11 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 1 0 30 29 28 27 26 25 24 23 22 21 p50/intp1/si11/sda11 p30/intp3/rtc1hz/sck11/scl11 p70/kr0/sck21/scl21 p71/kr1/si21/sda21 p72/kr2/so21 p73/kr3 p31/ti03/to03/intp4/pclbuz0 p62 p61/sdaa0 p60/scla0 p26/ani6 p25/ani5 p24/ani4 p23/ani3 p22/ani2 p21/ani1/av refm p20/ani0/av refp p01/to00/rxd1 p00/ti00/txd1 p120/ani19 exposed die pad rl78/g13 (top view) p147/ani18 p10/sck00/scl00/(ti07)/(to07) p11/si00/rxd0/toolrxd/sda00/(ti06)/(to06) p12/so00/txd0/tooltxd/(ti05)/(to05) p13/txd2/so20/(sdaa0)/(ti04)/(to04) p14/rxd2/si20/sda20/(scla0)/(ti03)/(to03) p15/pclbuz1/sck20/scl20/(ti02)/(to02) p16/ti01/to01/intp5/(rxd0) p17/ti02/to02/(txd0) p51/intp2/so11 p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd index mark caution connect the regc pin to vss via a capacitor (0.47 to 1 ? f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via setting s in the peripheral i/o redirection register (pior). refer to figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g13 user?s manual. 3. it is recommended to connect an exposed die pad to v ss .
rl78/g13 1. outline page 23 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.3.8 44-pin products ? 44-pin plastic lqfp (10 10 mm, 0.8 mm pitch) 33 32 31 30 29 28 27 26 25 24 23 rl78/g13 (top view) 1 2 3 4 5 6 7 8 9 10 11 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 p27/ani7 p26/ani6 p25/ani5 p24/ani4 p23/ani3 p22/ani2 p21/ani1/av refm p20/ani0/av refp p01/to00/rxd1 p00/ti00/txd1 p120/ani19 p147/ani18 p146 p10/sck00/scl00/(ti07)/(to07) p11/si00/rxd0/toolrxd/sda00/(ti06)/(to06) p12/so00/txd0/tooltxd/(ti05)/(to05) p13/txd2/so20/(sdaa0)/(ti04)/(to04) p14/rxd2/si20/sda20/(scla0)/(ti03)/(to03) p15/pclbuz1/sck20/scl20/(ti02)/(to02) p16/ti01/to01/intp5/(rxd0) p17/ti02/to02/(txd0) p51/intp2/so11 p41/ti07/to07 p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p50/intp1/si11/sda11 p30/intp3/rtc1hz/sck11/scl11 p70/kr0/sck21/scl21 p71/kr1/si21/sda21 p72/kr2/so21 p73/kr3 p31/ti03/to03/intp4/pclbuz0 p63 p62 p61/sdaa0 p60/scla0 caution connect the regc pin to vss via a capacitor (0.47 to 1 ? f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via setting s in the peripheral i/o redirection register (pior). refer to figure 4-8 format of periphe ral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 24 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.3.9 48-pin products ? 48-pin plastic lfqfp (7 7 mm, 0.5 mm pitch) 36 35 34 33 32 31 30 29 28 27 26 25 rl78/g13 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 p120/ani19 p41/ti07/to07 p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p140/pclbuz0/intp6 p00/ti00/txd1 p01/to00/rxd1 p130 p20/ani0/av refp p21/ani1/av refm p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 p147/ani18 p146 p10/sck00/scl00/(ti07)/(to07) p11/si00/rxd0/toolrxd/sda00/(ti06)/(to06) p12/so00/txd0/tooltxd/(ti05)/(to05) p13/txd2/so20/(sdaa0)/(ti04)/(to04) p14/rxd2/si20/sda20/(scla0)/(ti03)/(to03) p15/pclbuz1/sck20/scl20/(ti02)/(to02) p16/ti01/to01/intp5/(rxd0) p17/ti02/to02/(txd0) p51/intp2/so11 p50/intp1/si11/sda11 p60/scla0 p61/sdaa0 p62 p63 p31/ti03/to03/intp4/(pclbuz0) p75/kr5/intp9/sck01/scl01 p74/kr4/intp8/si01/sda01 p73/kr3/so01 p72/kr2/so21 p71/kr1/si21/sda21 p70/kr0/sck21/scl21 p30/intp3/rtc1hz/sck11/scl11 caution connect the regc pin to vss via a capacitor (0.47 to 1 ? f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via setting s in the peripheral i/o redirection register (pior). refer to figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 25 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 ? 48-pin plastic hwqfn (7 7 mm, 0.5 mm pitch) 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 p147/ani18 p146 p10/sck00/scl00/(ti07)/(to07) p11/si00/rxd0/toolrxd/sda00/(ti06)/(to06) p12/so00/txd0/tooltxd/(ti05)/(to05) p13/txd2/so20/(sdaa0)/(ti04)/(to04) p14/rxd2/si20/sda20/(scla0)/(ti03)/(to03) p15/pclbuz1/sck20/scl20/(ti02)/(to02) p16/ti01/to01/intp5/(rxd0) p17/ti02/to02/(txd0) p51/intp2/so11 p50/intp1/si11/sda11 p120/ani19 p41/ti07/to07 p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p140/pclbuz0/intp6 p00/ti00/txd1 p01/to00/rxd1 p130 p20/ani0/av refp p21/ani1/av refm p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 p60/scla0 p61/sdaa0 p62 p63 p31/ti03/to03/intp4/(pclbuz0) p75/kr5/intp9/sck01/scl01 p74/kr4/intp8/si01/sda01 p73/kr3/so01 p72/kr2/so21 p71/kr1/si21/sda21 p70/kr0/sck21/scl21 p30/intp3/rtc1hz/sck11/scl11 exposed die pad rl78/g13 (top view) index mark caution connect the regc pin to vss via a capacitor (0.47 to 1 ? f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via setting s in the peripheral i/o redirection register (pior). refer to figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g13 user?s manual. 3. it is recommended to connect an exposed die pad to v ss .
rl78/g13 1. outline page 26 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.3.10 52-pin products ? 52-pin plastic lqfp (10 10 mm, 0.65 mm pitch) 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 rl78/g13 (top view) p27/ani7 p26/ani6 p25/ani5 p24/ani4 p23/ani3 p22/ani2 p21/ani1/av refm p20/ani0/av refp p130 p03/ani16/rxd1 p02/ani17/txd1 p01/to00 p00/ti00 p140/pclbuz0/intp6 p120/ani19 p41/ti07/to07 p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p147/ani18 p146 p10/sck00/scl00/(ti07)/(to07) p11/si00/rxd0/toolrxd/sda00/(ti06)/(to06) p12/so00/txd0/tooltxd/(ti05)/(to05) p13/txd2/so20/(sdaa0)/(ti04)/(to04) p14/rxd2/si20/sda20/(scla0)/(ti03)/(to03) p15/pclbuz1/sck20/scl20/(ti02)/(to02) p16/ti01/to01/intp5/(rxd0) p17/ti02/to02/(txd0) p51/intp2/so11 p50/intp1/si11/sda11 p30/intp3/rtc1hz/sck11/scl11 p70/kr0/sck21/scl21 p71/kr1/si21/sda21 p72/kr2/so21 p73/kr3/so01 p74/kr4/intp8/si01/sda01 p75/kr5/intp9/sck01/scl01 p76/kr6/intp10/(rxd2) p77/kr7/intp11/(txd2) p31/ti03/to03/intp4/(pclbuz0) p63 p62 p61/sdaa0 p60/scla0 26 25 24 23 22 21 20 19 18 17 16 15 14 40 41 42 43 44 45 46 47 48 49 50 51 52 caution connect the regc pin to vss via a capacitor (0.47 to 1 ? f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via setting s in the peripheral i/o redirection register (pior). refer to figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 27 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.3.11 64-pin products ? 64-pin plastic lqfp (12 12 mm, 0.65 mm pitch) ? 64-pin plastic lfqfp (10 10 mm, 0.5 mm pitch) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 rl78/g13 (top view) p27/ani7 p26/ani6 p25/ani5 p24/ani4 p23/ani3 p22/ani2 p21/ani1/av refm p20/ani0/av refp p130 p04/sck10/scl10 p03/ani16/si10/rxd1/sda10 p02/ani17/so10/txd1 p01/to00 p00/ti00 p141/pclbuz1/intp7 p140/pclbuz0/intp6 p30/intp3/rtc1hz/sck11/scl11 p05/ti05/to05 p06/ti06/to06 p70/kr0/sck21/scl21 p71/kr1/si21/sda21 p72/kr2/so21 p73/kr3/so01 p74/kr4/intp8/si01/sda01 p75/kr5/intp9/sck01/scl01 p76/kr6/intp10/(rxd2) p77/kr7/intp11/(txd2) p31/ti03/to03/intp4/(pclbuz0) p63 p62 p61/sdaa0 p60/scla0 p147/ani18 p146 p10/sck00/scl00/(ti07)/(to07) p11/si00/rxd0/toolrxd/sda00/(ti06)/(to06) p12/so00/txd0/tooltxd/(intp5)/(ti05)/(to05) p13/txd2/so20/(sdaa0)/(ti04)/(to04) p14/rxd2/si20/sda20/(scla0)/(ti03)/(to03) p15/sck20/scl20/(ti02)/(to02) p16/ti01/to01/intp5/(si00)/(rxd0) p17/ti02/to02/(so00)/(txd0) p55/(pclbuz1)/(sck00) p54 p53/(intp11) p52/(intp10) p51/intp2/so11 p50/intp1/si11/sda11 p120/ani19 p43 p42/ti04/to04 p41/ti07/to07 p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss ev ss0 v dd ev dd0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 cautions 1. make ev ss0 pin the same potential as v ss pin. 2. make v dd pin the potential that is higher than ev dd0 pin. 3. connect the regc pin to vss via a capacitor (0.47 to 1 ? f). remarks 1. for pin identification, see 1.4 pin identification . 2. when using the microcontroller for an applicat ion where the noise generated inside the microcontroller must be reduced, it is reco mmended to supply separate powers to the v dd and ev dd0 pins and connect the v ss and ev ss0 pins to separate ground lines. 3. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8 format of periphe ral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 28 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 ? 64-pin plastic vfbga (4 4 mm, 0.4 mm pitch) 1 hgfedcba 2 3 4 5 6 7 8 abcdefgh top view rl78/g13 (top view) bottom view index mark pin no. name pin no. name pin no. name pin no. name a1 p05/ti05/to05 c1 p51/intp2/so11 e1 p13/txd2/so20/ (sdaa0)/(ti04)/(to04) g1 p146 a2 p30/intp3/rtc1hz /sck11/scl11 c2 p71/kr1/si21/sda21 e2 p14/rxd2/si20/sda20 /(scla0)/(ti03)/(to03) g2 p25/ani5 a3 p70/kr0/sck21 /scl21 c3 p74/kr4/intp8/si01 /sda01 e3 p15/sck20/scl20/ (ti02)/(to02) g3 p24/ani4 a4 p75/kr5/intp9 /sck01/scl01 c4 p52/(intp10) e4 p16/ti01/to01/intp5 /(si00)/(rxd0) g4 p22/ani2 a5 p77/kr7/intp11/ (txd2) c5 p53/(intp11) e5 p03/ani16/si10/rxd1 /sda10 g5 p130 a6 p61/sdaa0 c6 p63 e6 p41/ti07/to07 g6 p02/ani17/so10/txd1 a7 p60/scla0 c7 v ss e7 reset g7 p00/ti00 a8 ev dd0 c8 p121/x1 e8 p137/intp0 g8 p124/xt2/exclks b1 p50/intp1/si11 /sda11 d1 p55/(pclbuz1)/ (sck00) f1 p10/sck00/scl00/ (ti07)/(to07) h1 p147/ani18 b2 p72/kr2/so21 d2 p06/ti06/to06 f2 p11/si00/rxd0 /toolrxd/sda00/ (ti06)/(to06) h2 p27/ani7 b3 p73/kr3/so01 d3 p17/ti02/to02/ (so00)/(txd0) f3 p12/so00/txd0 /tooltxd/(intp5)/ (ti05)/(to05) h3 p26/ani6 b4 p76/kr6/intp10/ (rxd2) d4 p54 f4 p21/ani1/av refm h4 p23/ani3 b5 p31/ti03/to03 /intp4/(pclbuz0) d5 p42/ti04/to04 f5 p04/sck10/scl10 h5 p20/ani0/av refp b6 p62 d6 p40/tool0 f6 p43 h6 p141/pclbuz1/intp7 b7 v dd d7 regc f7 p01/to00 h7 p140/pclbuz0/intp6 b8 ev ss0 d8 p122/x2/exclk f8 p123/xt1 h8 p120/ani19 cautions 1. make ev ss0 pin the same potential as v ss pin. 2. make v dd pin the potential that is higher than ev dd0 pin. 3. connect the regc pin to vss via a capacitor (0.47 to 1 ? f). remarks 1. for pin identification, see 1.4 pin identification . 2. when using the microcontroller for an applicat ion where the noise generated inside the microcontroller must be reduced, it is reco mmended to supply separate powers to the v dd and ev dd0 pins and connect the v ss and ev ss0 pins to separate ground lines. 3. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8 format of periphe ral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 29 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.3.12 80-pin products ? 80-pin plastic lqfp (14 14 mm, 0.65 mm pitch) ? 80-pin plastic lfqfp (12 12 mm, 0.5 mm pitch) p152/ani10 p151/ani9 p150/ani8 p27/ani7 p26/ani6 p25/ani5 p24/ani4 p23/ani3 p22/ani2 p21/ani1/av refm p20/ani0/av refp p130 p04/sck10/scl10 p03/ani16/si10/rxd1/sda10 p02/ani17/so10/txd1 p01/to00 p00/ti00 p144/so30/txd3 p143/si30/rxd3/sda30 p142/sck30/scl30 p153/ani11 p100/ani20 p147/ani18 p146 p111/(intp11) p110/(intp10) p10/sck00/scl00/(ti07)/(to07) p11/si00/rxd0/toolrxd/sda00/(ti06)/(to06) p12/so00/txd0/tooltxd/(intp5)/(ti05)/(to05) p13/txd2/so20/(sdaa0)/(ti04)/(to04) p14/rxd2/si20/sda20/(scla0)/(ti03)/(to03) p15/sck20/scl20/(ti02)/(to02) p16/ti01/to01/intp5/(si00)/(rxd0) p17/ti02/to02/(so00)/(txd0) p55/(pclbuz1)/(sck00) p54/sck31/scl31 p53/si31/sda31 p52/so31 p51/intp2/so11 p50/intp1/si11/sda11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 rl78/g13 (top view) p30/intp3/rtc1hz/sck11/scl11 p05/ti05/to05 p06/ti06/to06 p70/kr0/sck21/scl21 p71/kr1/si21/sda21 p72/kr2/so21 p73/kr3 p74/kr4/intp8 p75/kr5/intp9 p76/kr6/intp10/(rxd2) p77/kr7/intp11/(txd2) p67/ti13/to13 p66/ti12/to12 p65/ti11/to11 p64/ti10/to10 p31/ti03/to03/intp4/(pclbuz0) p63/sdaa1 p62/scla1 p61/sdaa0 p60/scla0 p141/pclbuz1/intp7 p140/pclbuz0/intp6 p120/ani19 p45/so01 p44/si01/sda01 p43/sck01/scl01 p42/ti04/to04 p41/ti07/to07 p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss ev ss0 v dd ev dd0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 cautions 1. make ev ss0 pin the same potential as v ss pin. 2. make v dd pin the potential that is higher than ev dd0 pin. 3. connect the regc pin to vss via a capacitor (0.47 to 1 ? f). remarks 1. for pin identification, see 1.4 pin identification . 2. when using the microcontroller for an applicat ion where the noise generated inside the microcontroller must be reduced, it is reco mmended to supply separate powers to the v dd and ev dd0 pins and connect the v ss and ev ss0 pins to separate ground lines. 3. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8 format of periphe ral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 30 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.3.13 100-pin products ? 100-pin plastic lqfp (14 14 mm, 0.5 mm pitch) p142/sck30/scl30 p141/pclbuz1/intp7 p140/pclbuz0/intp6 p120/ani19 p47/intp2 p46/intp1/ti05/to05 p45/so01 p44/si01/sda01 p43/sck01/scl01 p42/ti04/to04 p41 p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss ev ss0 v dd ev dd0 p60/scla0 p61/sdaa0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p100/ani20 p147/ani18 p146/(intp4) p111/(intp11) p110/(intp10) p101 p10/sck00/scl00/(ti07)/(to07) p11/si00/rxd0/toolrxd/sda00/(ti06)/(to06) p12/so00/txd0/tooltxd/(intp5)/(ti05)/(to05) p13/txd2/so20/(sdaa0)/(ti04)/(to04) p14/rxd2/si20/sda20/(scla0)/(ti03)/(to03) p15/sck20/scl20/(ti02)/(to02) p16/ti01/to01/intp5/(si00)/(rxd0) p17/ti02/to02/(so00)/(txd0) p57/(intp3) p56/(intp1) p55/(pclbuz1)/(sck00) p54/sck31/scl31 p53/si31/sda31 p52/so31 p51/so11 p50/si11/sda11 ev dd1 p30/intp3/rtc1hz/sck11/scl11 p87/(intp9) p156/ani14 p155/ani13 p154/ani12 p153/ani11 p152/ani10 p151/ani9 p150/ani8 p27/ani7 p26/ani6 p25/ani5 p24/ani4 p23/ani3 p22/ani2 p21/ani1/av refm p20/ani0/av refp p130 p102/ti06/to06 p04/sck10/scl10 p03/ani16/si10/rxd1/sda10 p02/ani17/so10/txd1 p01/to00 p00/ti00 p145/ti07/to07 p144/so30/txd3 p143/si30/rxd3/sda30 p86/(intp8) p85/(intp7) p84/(intp6) p83 p82/(so10)/(txd1) p81/(si10)/(rxd1)/(sda10) p80/(sck10)/(scl10) ev ss1 p05 p06 p70/kr0/sck21/scl21 p71/kr1/si21/sda21 p72/kr2/so21 p73/kr3 p74/kr4/intp8 p75/kr5/intp9 p76/kr6/intp10/(rxd2) p77/kr7/intp11/(txd2) p67/ti13/to13 p66/ti12/to12 p65/ti11/to11 p64/ti10/to10 p31/ti03/to03/intp4/(pclbuz0) p63/sdaa1 p62/scla1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 rl78/g13 (top view) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 cautions 1. make ev ss0 , ev ss1 pins the same potential as v ss pin. 2. make v dd pin the potential that is higher than ev dd0 , ev dd1 pins (ev dd0 = ev dd1 ). 3. connect the regc pin to vss via a capacitor (0.47 to 1 ? f). remarks 1. for pin identification, see 1.4 pin identification . 2. when using the microcontroller for an applicat ion where the noise generated inside the microcontroller must be reduced, it is re commended to supply separate powers to the v dd , ev dd0 and ev dd1 pins and connect the v ss , ev ss0 and ev ss1 pins to separate ground lines. 3. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8 format of periphe ral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 31 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 ? 100-pin plastic lqfp (14 20 mm, 0.65 mm pitch) p140/pclbuz0/intp6 p141/pclbuz1/intp7 p142/sck30/scl30 p143/si30/rxd3/sda30 p144/so30/txd3 p145/ti07/to07 p00/ti00 p01/to00 p02/ani17/so10/txd1 p03/ani16/si10/rxd1/sda10 p04/sck10/scl10 p102/ti06/to06 p130 p20/ani0/av refp p21/ani1/av refm p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 p150/ani8 p151/ani9 p152/ani10 p153/ani11 p154/ani12 p155/ani13 p156/ani14 p100/ani20 p147/ani18 p60/scla0 p61/sdaa0 p62/scla1 p63/sdaa1 p31/ti03/to03/intp4/(pclbuz0) p64/ti10/to10 p65/ti11/to11 p66/ti12/to12 p67/ti13/to13 p77/kr7/intp11/(txd2) p76/kr6/intp10/(rxd2) p75/kr5/intp9 p74/kr4/intp8 p73/kr3 p72/kr2/so21 p71/kr1/si21/sda21 p70/kr0/sck21/scl21 p06 p05 ev ss1 p80/(sck10)/(scl10) p81/(si10)/(rxd1)/(sda10) p82/(so10)/(txd1) p83 p84/(intp6) p85/(intp7) p86/(intp8) p87/(intp9) p30/intp3/rtc1hz/sck11/scl11 ev dd1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 rl78/g13 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p146/(intp4) p111/(intp11) p110/(intp10) p101 p10/sck00/scl00/(ti07)/(to07) p11/si00/rxd0/toolrxd/sda00/(ti06)/(to06) p12/so00/txd0/tooltxd/(intp5)/(ti05)/(to05) p13/txd2/so20/(sdaa0)/(ti04)/(to04) p14/rxd2/si20/sda20/(scla0)/(ti03)/(to03) p15/sck20/scl20/(ti02)/(to02) p16/ti01/to01/intp5/(si00)/(rxd0) p17/ti02/to02/(so00)/(txd0) p57/(intp3) p56/(intp1) p55/(pclbuz1)/(sck00) p54/sck31/scl31 p53/si31/sda31 p52/so31 p51/so11 p50/si11/sda11 p120/ani19 p47/intp2 p46/intp1/ti05/to05 p45/so01 p44/si01/sda01 p43/sck01/scl01 p42/ti04/to04 p41 p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss ev ss0 v dd ev dd0 cautions 1. make ev ss0 , ev ss1 pins the same potential as v ss pin. 2. make v dd pin the potential that is higher than ev dd0 , ev dd1 pins (ev dd0 = ev dd1 ). 3. connect the regc pin to vss via a capacitor (0.47 to 1 ? f). remarks 1. for pin identification, see 1.4 pin identification . 2. when using the microcontroller for an applicat ion where the noise generated inside the microcontroller must be reduced, it is re commended to supply separate powers to the v dd , ev dd0 and ev dd1 pins and connect the v ss , ev ss0 and ev ss1 pins to separate ground lines. 3. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8 format of periphe ral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 32 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.3.14 128-pin products ? 128-pin plastic lfqfp (14 20 mm, 0.5 mm pitch) p100/ani20 p147/ani18 p146/(intp4) p111/(intp11) p110/(intp10) p101 p117/ani24 p116/ani25 p115/ani26 p114 p113 p112 p97/so11 p96/si11/sda11 p95/sck11/scl11 p94 p93 p92 p91 p90 p10/sck00/scl00/(ti07)/(to07) p11/si00/rxd0/toolrxd/sda00/(ti06)/(to06) p12/so00/txd0/tooltxd/(intp5)/(ti05)/(to05) p13/txd2/so20/(sdaa0)/(ti04)/(to04) p14/rxd2/si20/sda20/(scla0)/(ti03)/(to03) p15/sck20/scl20/(ti02)/(to02) p16/ti01/to01/intp5/(si00)/(rxd0) p17/ti02/to02/(so00)/(txd0) p57/(intp3) p56/(intp1) p55/(pclbuz1)/(sck00) p54/sck31/scl31 p53/si31/sda31 p52/so31 p51 p50 p30/intp3/rtc1hz p87/(intp9) p142/sck30/scl30 p141/pclbuz1/intp7 p140/pclbuz0/intp6 p120/ani19 p37/ani21 p36/ani22 p35/ani23 p34 p33 p32 p106/ti17/to17 p105/ti16/to16 p104/ti15/to15 p103/ti14/to14 p47/intp2 p46/intp1/ti05/to05 p45/so01 p44/si01/sda01 p43/sck01/scl01 p42/ti04/to04 p41 p40/tool0 p127 p126 p125 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss ev ss0 v dd ev dd0 p60/scla0 p61/sdaa0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 rl78/g13 (top view) 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 p86/(intp8) p85/(intp7) p84/(intp6) p83 p82/(so10)/(txd1) p81/(si10)/(rxd1)/(sda10) p80/(sck10)/(scl10) ev dd1 ev ss1 p05 p06 p70/kr0/sck21/scl21 p71/kr1/si21/sda21 p72/kr2/so21 p73/kr3 p74/kr4/intp8 p75/kr5/intp9 p76/kr6/intp10/(rxd2) p77/kr7/intp11/(txd2) p67/ti13/to13 p66/ti12/to12 p65/ti11/to11 p64/ti10/to10 p31/ti03/to03/intp4/(pclbuz0) p63/sdaa1 p62/scla1 p156/ani14 p155/ani13 p154/ani12 p153/ani11 p152/ani10 p151/ani9 p150/ani8 p27/ani7 p26/ani6 p25/ani5 p24/ani4 p23/ani3 p22/ani2 p21/ani1/av refm p20/ani0/av refp p130 p102/ti06/to06 p07 p04/sck10/scl10 p03/ani16/si10/rxd1/sda10 p02/ani17/so10/txd1 p01/to00 p00/ti00 p145/ti07/to07 p144/so30/txd3 p143/si30/rxd3/sda30 cautions 1. make ev ss0 , ev ss1 pins the same potential as v ss pin. 2. make v dd pin the potential that is higher than ev dd0 , ev dd1 pins (ev dd0 = ev dd1 ). 3. connect the regc pin to vss via a capacitor (0.47 to 1 ? f). remarks 1. for pin identification, see 1.4 pin identification . 2. when using the microcontroller for an applicat ion where the noise generated inside the microcontroller must be reduced, it is re commended to supply separate powers to the v dd , ev dd0 and ev dd1 pins and connect the v ss , ev ss0 and ev ss1 pins to separate ground lines. 3. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8 format of periphe ral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 33 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.4 pin identification ani0 to ani14, ani16 to ani26: analog input av refm : a/d converter reference potential ( ? side) input av refp : a/d converter reference potential (+ side) input ev dd0 , ev dd1 : power supply for port ev ss0 , ev ss1 : ground for port exclk: external clock input (main system clock) exclks: external clock input (subsystem clock) intp0 to intp11: interrupt request from peripheral kr0 to kr7: key return p00 to p07: port 0 p10 to p17: port 1 p20 to p27: port 2 p30 to p37: port 3 p40 to p47: port 4 p50 to p57: port 5 p60 to p67: port 6 p70 to p77: port 7 p80 to p87: port 8 p90 to p97: port 9 p100 to p106: port 10 p110 to p117: port 11 p120 to p127: port 12 p130, p137: port 13 p140 to p147: port 14 p150 to p156: port 15 pclbuz0, pclbuz1: programmable clock output/buzzer output regc: regulator capacitance reset: reset rtc1hz: real-time cloc k correction clock (1 hz) output rxd0 to rxd3: receive data sck00, sck01, sck10, sck11, sck20, sck21, scla0, scla1: serial clock input/output scla0, scla1, scl00, scl01, scl10, scl11, scl20,scl21, scl30, scl31: serial clock output sdaa0, sdaa1, sda00, sda01,sda10, sda11, sda20,sda21, sda30, sda31: serial data input/output si00, si01, si10, si11, si20, si21, si30, si31: serial data input so00, so01, so10, so11, so20, so21, so30, so31: serial data output ti00 to ti07, ti10 to ti17: timer input to00 to to07, to10 to to17: timer output tool0: data input/output for tool toolrxd, tooltxd: data inpu t/output for external device txd0 to txd3: transmit data v dd : power supply v ss : ground x1, x2: crystal oscillator (main system clock) xt1, xt2: crystal oscillator (subsystem clock)
rl78/g13 1. outline page 34 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.5 block diagram 1.5.1 20-pin products port 1 p10 to p12, p16, p17 port 2 p20 to p22 3 port 3 p30 port 4 5 port 12 p121, p122 p40 voltage regulator regc interrupt control ram low-speed on-chip oscillator power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11 txd0/p12 rxd1/p01 txd1/p00 scl00/p10 sda00/p11 timer array unit (8ch) ch2 ti02/to02/p17 ch3 ch0 ch1 ch4 ch5 ch6 ch7 intp0/p137 intp3/p30 a/d converter 3 ani0/p20 to ani2/p22 av refp /p20 av refm /p21 2 port 13 p137 csi11 sck11/p30 so11/p16 si11/p17 iic11 scl11/p30 sda11/p17 ti00/p00 to00/p01 bcd adjustment 12-bit interval timer sck00/p10 so00/p12 si00/p11 csi00 v ss toolrxd/p11, tooltxd/p12 v dd intp5/p16 port 0 p00, p01 2 window watchdog timer real-time clock 3 ani16/p01, ani17/p00, ani18/p147 direct memory access control port 14 p147 ti01/to01/p16 multiplier& divider, mulitiply- accumulator rl78 cpu core code flash memory data flash memory crc
rl78/g13 1. outline page 35 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.5.2 24-pin products port 1 p10 to p12, p16, p17 port 2 p20 to p22 3 port 3 p30, p31 2 port 4 port 5 5 port 12 p121, p122 p40 p50 voltage regulator regc interrupt control ram window watchdog timer power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11 txd0/p12 rxd1/p01 txd1/p00 scl00/p10 sda00/p11 timer array unit (8ch) ch2 ti02/to02/p17 ch3 ti03/to03/p31 ch0 ch1 ch4 ch5 ch6 ch7 intp0/p137 intp3/p30, intp4/p31 intp1/p50 a/d converter 3 ani0/p20 to ani2/p22 av refp /p20 av refm /p21 2 port 13 p137 csi11 sck11/p30 so11/p17 si11/p50 iic11 scl11/p30 sda11/p50 ti00/p00 to00/p01 bcd adjustment sck00/p10 so00/p12 si00/p11 csi00 v ss toolrxd/p11, tooltxd/p12 v dd serial interface iica0 sdaa0/p61 scla0/p60 2 intp5/p16 multiplier& divider, mulitiply- accumulator port 0 p00, p01 2 3 ani16/p01, ani17/p00, ani18/p147 direct memory access control port 6 p60, p61 2 port 14 p147 ti01/to01/p16 buzzer output pclbuz0/p31 clock output control real-time clock rl78 cpu core code flash memory data flash memory crc low-speed on-chip oscillator 12-bit interval timer
rl78/g13 1. outline page 36 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.5.3 25-pin products port 1 p10 to p12, p16, p17 port 2 p20 to p22 3 port 3 p30, p31 2 port 4 port 5 5 port 12 p121, p122 p40 p50 voltage regulator regc interrupt control ram power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11 txd0/p12 rxd1/p01 txd1/p00 scl00/p10 sda00/p11 timer array unit (8ch) ch2 ti02/to02/p17 ch3 ti03/to03/p31 ch0 ch1 ch4 ch5 ch6 ch7 intp0/p137 intp3/p30, intp4/p31 intp1/p50 a/d converter 3 ani0/p20 to ani2/p22 av refp /p20 av refm /p21 2 port 13 p137 p130 csi11 sck11/p30 so11/p17 si11/p50 iic11 scl11/p30 sda11/p50 ti00/p00 to00/p01 bcd adjustment sck00/p10 so00/p12 si00/p11 csi00 v ss toolrxd/p11, tooltxd/p12 v dd serial interface iica0 sdaa0/p61 scla0/p60 2 intp5/p16 multiplier& divider, mulitiply- accumulator port 0 p00, p01 2 3 ani16/p01, ani17/p00, ani18/p147 direct memory access control port 6 p60, p61 2 port 14 p147 ti01/to01/p16 buzzer output pclbuz0/p31 clock output control window watchdog timer real-time clock rl78 cpu core code flash memory data flash memory low-speed on-chip oscillator 12-bit interval timer crc
rl78/g13 1. outline page 37 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.5.4 30-pin products port 1 p10 to p17 port 2 p20 to p23 4 port 3 p30, p31 2 port 4 port 5 8 port 12 p121, p122 p40 p50, p51 2 voltage regulator regc interrupt control ram power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11(rxd0/p16) txd0/p12(txd0/p17) rxd1/p01 txd1/p00 scl00/p10 sda00/p11 timer array unit (8ch) ch2 ti02/to02/p17 (ti02/to02/p15) ch3 ti03/to03/p31 (ti03/to03/p14) ch0 ch1 ch4 ch5 ch6 ch7 2 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 rxd2/p14 a/d converter 4 ani0/p20 to ani3/p23 av refp /p20 av refm /p21 2 p120 port 13 p137 csi11 sck11/p30 so11/p51 si11/p50 iic11 scl11/p30 sda11/p50 ti00/p00 to00/p01 bcd adjustment sck00/p10 so00/p12 si00/p11 csi00 v ss toolrxd/p11, tooltxd/p12 v dd serial interface iica0 sdaa0/p61(sdaa0/p13) scla0/p60(scla0/p14) 2 intp5/p16 multiplier& divider, mulitiply- accumulator port 0 p00, p01 2 buzzer output clock output control 4 ani16/p01, ani17/p00, ani18/p147, ani19/p120 serial array unit1 (2ch) uart2 linsel iic20 rxd2/p14 txd2/p13 scl20/p15 sda20/p14 sck20/p15 so20/p13 si20/p14 csi20 direct memory access control port 6 p60, p61 2 port 14 p147 ti01/to01/p16 rxd2/p14 pclbuz0/p31, pclbuz1/p15 2 window watchdog timer real-time clock rl78 cpu core code flash memory data flash memory (ti04/to04/p13) (ti05/to05/p12) (ti06/to06/p11) (ti07/to07/p10) crc low-speed on-chip oscillator 12-bit interval timer remark functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 38 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.5.5 32-pin products port 1 p10 to p17 port 2 p20 to p23 4 port 3 p30, p31 2 port 4 port 5 8 port 12 p121, p122 p40 p50, p51 2 voltage regulator regc interrupt control ram power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11(rxd0/p16) txd0/p12(txd0/p17) rxd1/p01 txd1/p00 scl00/p10 sda00/p11 timer array unit (8ch) ch2 ti02/to02/p17 (ti02/to02/p15) ch3 ti03/to03/p31 (ti03/to03/p14) ch0 ch1 ch4 ch5 ch6 ch7 2 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 rxd2/p14 a/d converter 4 ani0/p20 to ani3/p23 av refp /p20 av refm /p21 2 p120 port 13 p137 csi11 sck11/p30 so11/p51 si11/p50 iic11 scl11/p30 sda11/p50 ti00/p00 to00/p01 bcd adjustment sck00/p10 so00/p12 si00/p11 csi00 v ss toolrxd/p11, tooltxd/p12 v dd serial interface iica0 sdaa0/p61(sdaa0/p13) scla0/p60(scla0/p14) 2 intp5/p16 multiplier& divider, mulitiply- accumulator port 0 p00, p01 2 buzzer output clock output control 4 ani16/p01, ani17/p00, ani18/p147, ani19/p120 serial array unit1 (2ch) uart2 linsel iic20 rxd2/p14 txd2/p13 scl20/p15 sda20/p14 sck20/p15 so20/p13 si20/p14 csi20 direct memory access control port 6 port 7 p70 p60 to p62 3 port 14 p147 ti01/to01/p16 rxd2/p14 pclbuz0/p31, pclbuz1/p15 2 window watchdog timer real-time clock rl78 cpu core code flash memory data flash memory (ti04/to04/p13) (ti05/to05/p12) (ti06/to06/p11) (ti07/to07/p10) low-speed on-chip oscillator 12-bit interval timer crc remark functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 39 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.5.6 36-pin products port 1 p10 to p17 port 2 p20 to p25 6 port 3 p30, p31 2 port 4 port 5 8 port 12 p121, p122 p40 p50, p51 2 voltage regulator regc interrupt control ram power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11(rxd0/p16) txd0/p12(txd0/p17) rxd1/p01 txd1/p00 scl00/p10 sda00/p11 timer array unit (8ch) ch2 ti02/to02/p17 (ti02/to02/p15) ch3 ti03/to03/p31 (ti03/to03/p14) ch0 ch1 ch4 ch5 ch6 ch7 2 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 rxd2/p14 a/d converter 6 ani0/p20 to ani5/p25 av refp /p20 av refm /p21 2 p120 port 13 p137 csi11 sck11/p30 so11/p51 si11/p50 iic11 scl11/p30 sda11/p50 ti00/p00 to00/p01 bcd adjustment sck00/p10 so00/p12 si00/p11 csi00 v ss toolrxd/p11, tooltxd/p12 v dd serial interface iica0 sdaa0/p61(sdaa0/p13) scla0/p60(scla0/p14) 2 intp5/p16 multiplier& divider, mulitiply- accumulator port 0 p00, p01 2 buzzer output clock output control real-time clock window watchdog timer 2 ani18/p147, ani19/p120 serial array unit1 (2ch) uart2 linsel iic20 rxd2/p14 txd2/p13 scl20/p15 sda20/p14 iic21 scl21/p70 sda21/p71 sck20/p15 so20/p13 si20/p14 csi20 sck21/p70 so21/p72 si21/p71 csi21 direct memory access control port 6 port 7 p70 to p72 3 p60 to p62 3 port 14 p147 ti01/to01/p16 rxd2/p14 pclbuz0/p31, pclbuz1/p15 2 rl78 cpu core code flash memory data flash memory (ti04/to04/p13) (ti05/to05/p12) (ti06/to06/p11) (ti07/to07/p10) low-speed on-chip oscillator 12-bit interval timer crc remark functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 40 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.5.7 40-pin products port 1 p10 to p17 port 2 p20 to p26 7 port 3 p30, p31 2 port 4 port 5 8 port 12 p121 to p124 p40 p50, p51 2 voltage regulator regc interrupt control ram window watchdog timer power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 real-time clock serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11(rxd0/p16) txd0/p12(txd0/p17) rxd1/p01 txd1/p00 scl00/p10 sda00/p11 timer array unit (8ch) ch2 ti02/to02/p17 (ti02/to02/p15) ch3 ti03/to03/p31 (ti03/to03/p14) ch0 ch1 ch4 ch5 ch6 ch7 2 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 rxd2/p14 a/d converter 7 ani0/p20 to ani6/p26 av refp /p20 av refm /p21 4 p120 port 13 p137 csi11 sck11/p30 so11/p51 si11/p50 iic11 scl11/p30 sda11/p50 ti00/p00 to00/p01 bcd adjustment sck00/p10 so00/p12 si00/p11 csi00 v ss toolrxd/p11, tooltxd/p12 v dd serial interface iica0 sdaa0/p61(sdaa0/p13) scla0/p60(scla0/p14) 2 intp5/p16 multiplier& divider, mulitiply- accumulator xt1/p123 xt2/exclks/p124 port 0 p00, p01 2 buzzer output clock output control key return 4 kr0/p70 to kr3/p73 2 ani18/p147, ani19/p120 serial array unit1 (2ch) uart2 linsel iic20 rxd2/p14 txd2/p13 scl20/p15 sda20/p14 iic21 scl21/p70 sda21/p71 sck20/p15 so20/p13 si20/p14 csi20 sck21/p70 so21/p72 si21/p71 csi21 direct memory access control port 6 port 7 p70 to p73 4 p60 to p62 3 port 14 p147 ti01/to01/p16 rtc1hz/p30 pclbuz0/p31, pclbuz1/p15 2 rl78 cpu core code flash memory data flash memory (ti04/to04/p13) (ti05/to05/p12) (ti06/to06/p11) rxd2/p14 (ti07/to07/p10) low-speed on-chip oscillator 12-bit interval timer crc remark functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 41 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.5.8 44-pin products port 1 p10 to p17 port 2 p20 to p27 8 port 3 p30, p31 2 port 4 port 5 8 port 12 p121 to p124 p40, p41 2 p50, p51 2 voltage regulator regc interrupt control ram window watchdog timer power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 real-time clock serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11(rxd0/p16) txd0/p12(txd0/p17) rxd1/p01 txd1/p00 scl00/p10 sda00/p11 timer array unit (8ch) ch2 ti02/to02/p17 (ti02/to02/p15) ch3 ti03/to03/p31 (ti03/to03/p14) ch0 ch1 ch4 ch5 ch6 ch7 2 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 rxd2/p14 a/d converter 8 ani0/p20 to ani7/p27 av refp /p20 av refm /p21 4 p120 port 13 p137 csi11 sck11/p30 so11/p51 si11/p50 iic11 scl11/p30 sda11/p50 ti07/to07/p41 (ti07/to07/p10) ti00/p00 to00/p01 bcd adjustment sck00/p10 so00/p12 si00/p11 csi00 v ss toolrxd/p11, tooltxd/p12 v dd serial interface iica0 sdaa0/p61(sdaa0/p13) scla0/p60(scla0/p14) 2 intp5/p16 multiplier& divider, mulitiply- accumulator xt1/p123 xt2/exclks/p124 port 0 p00, p01 2 buzzer output clock output control key return 4 kr0/p70 to kr3/p73 2 ani18/p147, ani19/p120 serial array unit1 (2ch) uart2 linsel iic20 rxd2/p14 txd2/p13 scl20/p15 sda20/p14 iic21 scl21/p70 sda21/p71 sck20/p15 so20/p13 si20/p14 csi20 sck21/p70 so21/p72 si21/p71 csi21 direct memory access control port 6 port 7 p70 to p73 4 p60 to p63 4 port 14 p146, p147 2 ti01/to01/p16 rtc1hz/p30 rxd2/p14 pclbuz0/p31, pclbuz1/p15 2 rl78 cpu core code flash memory data flash memory (ti04/to04/p13) (ti05/to05/p12) (ti06/to06/p11) low-speed on-chip oscillator 12-bit interval timer crc remark functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 42 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.5.9 48-pin products port 1 p10 to p17 port 2 p20 to p27 8 port 3 p30, p31 2 port 4 port 5 8 port 12 p121 to p124 p40, p41 2 p50, p51 2 voltage regulator regc interrupt control ram window watchdog timer power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11(rxd0/p16) txd0/p12(txd0/p17) rxd1/p01 txd1/p00 scl00/p10 sda00/p11 timer array unit (8ch) ch2 ti02/to02/p17 (ti02/to02/p15) ch3 ti03/to03/p31 (ti03/to03/p14) ch0 ch1 ch4 ch5 ch6 ch7 intp8/p74, intp9/p75 2 intp0/p137 intp3/p30, intp4/p31 intp6/p140 intp1/p50, intp2/p51 rxd2/p14 a/d converter 8 ani0/p20 to ani7/p27 av refp /p20 av refm /p21 4 p120 port 13 p130 p137 csi11 sck11/p30 so11/p51 si11/p50 iic01 scl01/p75 sda01/p74 iic11 scl11/p30 sda11/p50 ti07/to07/p41 (ti07/to07/p10) ti00/p00 to00/p01 bcd adjustment sck00/p10 so00/p12 si00/p11 csi00 v ss toolrxd/p11, tooltxd/p12 v dd serial interface iica0 sdaa0/p61(sdaa0/p13) scla0/p60(scla0/p14) 2 2 intp5/p16 multiplier& divider, mulitiply- accumulator xt1/p123 xt2/exclks/p124 port 0 p00, p01 2 buzzer output pclbuz0/p140 (pclbuz0/p31), pclbuz1/p15 clock output control key return 6 kr0/p70 to kr5/p75 2 ani18/p147, ani19/p120 sck01/p75 so01/p73 si01/p74 csi01 serial array unit1 (2ch) uart2 linsel iic20 rxd2/p14 txd2/p13 scl20/p15 sda20/p14 iic21 scl21/p70 sda21/p71 sck20/p15 so20/p13 si20/p14 csi20 sck21/p70 so21/p72 si21/p71 csi21 direct memory access control port 6 port 7 p70 to p75 6 p60 to p63 4 port 14 p140, p146, p147 3 2 ti01/to01/p16 rtc1hz/p30 rxd2/p14 real-time clock rl78 cpu core code flash memory data flash memory (ti04/to04/p13) (ti05/to05/p12) (ti06/to06/p11) low-speed on-chip oscillator 12-bit interval timer crc remark functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 43 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.5.10 52-pin products port 1 p10 to p17 port 2 p20 to p27 8 port 3 p30, p31 2 port 4 port 5 8 port 12 p121 to p124 p40, p41 2 p50, p51 2 voltage regulator regc interrupt control ram power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11(rxd0/p16) txd0/p12(txd0/p17) rxd1/p03 txd1/p02 scl00/p10 sda00/p11 timer array unit (8ch) ch2 ti02/to02/p17 (ti02/to02/p15) ch3 ti03/to03/p31 (ti03/to03/p14) ch0 ch1 ch4 ch5 ch6 ch7 intp8/p74 to intp11/p77 2 intp0/p137 intp3/p30, intp4/p31 intp6/p140 intp1/p50, intp2/p51 rxd2/p14 (rxd2/p76) a/d converter 8 ani0/p20 to ani7/p27 av refp /p20 av refm /p21 4 p120 port 13 p130 p137 csi11 sck11/p30 so11/p51 si11/p50 iic01 scl01/p75 sda01/p74 iic11 scl11/p30 sda11/p50 ti07/to07/p41 (ti07/to07/p10) ti00/p00 to00/p01 bcd adjustment sck00/p10 so00/p12 si00/p11 csi00 v ss toolrxd/p11, tooltxd/p12 v dd serial interface iica0 sdaa0/p61(sdaa0/p13) scla0/p60(scla0/p14) 4 2 intp5/p16 multiplier& divider, mulitiply- accumulator xt1/p123 xt2/exclks/p124 port 0 p00 to p03 4 buzzer output pclbuz0/p140 (pclbuz0/p31), pclbuz1/p15 clock output control key return 8 kr0/p70 to kr7/p77 window watchdog timer 4 ani16/p03, ani17/p02, ani18/p147, ani19/p120 sck01/p75 so01/p73 si01/p74 csi01 serial array unit1 (2ch) uart2 linsel iic20 rxd2/p14(rxd2/p76) txd2/p13(txd2/p77) scl20/p15 sda20/p14 iic21 scl21/p70 sda21/p71 sck20/p15 so20/p13 si20/p14 csi20 sck21/p70 so21/p72 si21/p71 csi21 direct memory access control port 6 port 7 p70 to p77 8 p60 to p63 4 port 14 p140, p146, p147 3 2 ti01/to01/p16 rtc1hz/p30 rxd2/p14 (rxd2/p76) real-time clock rl78 cpu core code flash memory data flash memory (ti04/to04/p13) (ti05/to05/p12) (ti06/to06/p11) low-speed on-chip oscillator 12-bit interval timer crc remark functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 44 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.5.11 64-pin products port 1 p10 to p17 port 2 p20 to p27 8 port 3 p30, p31 2 port 4 port 5 8 port 12 p121 to p124 p40 to p43 4 p50 to p55 6 voltage regulator regc interrupt control ram rl78 cpu core power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11(rxd0/p16) txd0/p12(txd0/p17) rxd1/p03 txd1/p02 scl00/p10 sda00/p11 timer array unit (8ch) ch2 ti02/to02/p17 (ti02/to02/p15) ch3 ti03/to03/p31 (ti03/to03/p14) ch0 ch1 ch4 ti04/to04/p42 (ti04/to04/p13) ch5 ti05/to05/p05 (ti05/to05/p12) ch6 ti06/to06/p06 (ti06/to06/p11) ch7 intp8/p74, intp9/p75 2 intp0/p137 intp3/p30, intp4/p31 intp6/p140, intp7/p141 intp1/p50, intp2/p51 rxd2/p14 (rxd2/p76) csi10 sck10/p04 so10/p02 si10/p03 a/d converter 8 ani0/p20 to ani7/p27 av refp /p20 av refm /p21 4 p120 port 13 p130 p137 csi11 sck11/p30 so11/p51 si11/p50 iic01 scl01/p75 sda01/p74 iic10 scl10/p04 sda10/p03 iic11 scl11/p30 sda11/p50 ti07/to07/p41 (ti07/to07/p10) ti00/p00 to00/p01 bcd adjustment sck00/p10(sck00/p55) so00/p12(so00/p17) si00/p11(si00/p16) csi00 v ss , ev ss0 toolrxd/p11, tooltxd/p12 v dd , ev dd0 serial interface iica0 sdaa0/p61(sdaa0/p13) scla0/p60(scla0/p14) 2 2 2 intp5/p16(intp5/p12) multiplier& divider, mulitiply- accumulator xt1/p123 xt2/exclks/p124 port 0 p00 to p06 7 buzzer output pclbuz0/p140 (pclbuz0/p31), pclbuz1/p141 (pclbuz1/p55) clock output control key return 8 kr0/p70 to kr7/p77 window watchdog timer 4 ani16/p03, ani17/p02, ani18/p147, ani19/p120 sck01/p75 so01/p73 si01/p74 csi01 serial array unit1 (2ch) uart2 linsel iic20 rxd2/p14(rxd2/p76) txd2/p13(txd2/p77) scl20/p15 sda20/p14 iic21 scl21/p70 sda21/p71 sck20/p15 so20/p13 si20/p14 csi20 sck21/p70 so21/p72 si21/p71 csi21 direct memory access control port 6 port 7 p70 to p77 8 p60 to p63 4 port 14 p140, p141, p146, p147 4 2 ti01/to01/p16 rtc1hz/p30 rxd2/p14 (rxd2/p76) real-time clock code flash memory data flash memory intp10/p76(intp10/p52), intp11/p77(intp11/p53) 2 low-speed on-chip oscillator crc 12-bit interval timer remark functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 45 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.5.12 80-pin products port 1 port 2 p20 to p27 8 port 3 p30, p31 2 port 4 port 5 p10 to p17 8 p40 to p45 6 p50 to p55 6 voltage regulator regc interrupt control ram window watchdog timer power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11(rxd0/p16) txd0/p12(txd0/p17) rxd1/p03 txd1/p02 scl00/p10 sda00/p11 timer array unit0 (8ch) ch2 ti02/to02/p17 (ti02/to02/p15) ch3 ti03/to03/p31 (ti03/to03/p14) ch0 ch1 ch4 ti04/to04/p42 (ti04/to04/p13) ch5 ti05/to05/p05 (ti05/to05/p12) ch6 ti06/to06/p06 (ti06/to06/p11) ch7 intp8/p74, intp9/p75 2 intp0/p137 intp3/p30, intp4/p31 intp6/p140, intp7/p141 intp1/p50, intp2/p51 rxd2/p14 (rxd2/p76) csi10 sck10/p04 so10/p02 si10/p03 a/d converter 8 ani0/p20 to ani7/p27 av refp /p20 av refm /p21 csi11 sck11/p30 so11/p51 si11/p50 iic01 scl01/p43 sda01/p44 iic10 scl10/p04 sda10/p03 iic11 scl11/p30 sda11/p50 ti07/to07/p41 (ti07/to07/p10) ti00/p00 to00/p01 bcd adjustment so00/p12(so00/p17) si00/p11(si00/p16) csi00 v ss , ev ss0 toolrxd/p11, tooltxd/p12 v dd , ev dd0 serial interface iica0 scla0/p60(scla0/p14) sdaa0/p61(sdaa0/p13) 2 2 2 intp5/p16(intp5/p12) multiplier& divider, mulitiply- accumulator xt1/p123 xt2/exclks/p124 port 0 p00 to p06 7 buzzer output pclbuz0/p140 (pclbuz0/p31), pclbuz1/p141 (pclbuz1/p55) clock output control key return 8 kr0/p70 to kr7/p77 5 ani16/p03, ani17/p02, ani18/p147, ani19/p120, ani20/p100 sck01/p43 so01/p45 si01/p44 csi01 direct memory access control port 6 port 7 p70 to p77 8 p60 to p67 8 port 10 p100 2 ti01/to01/p16 rtc1hz/p30 rxd2/p14 (rxd2/p76) 4 ani8/p150 to ani11/p153 port 11 p110, p111 2 port 12 p121 to p124 4 p120 port 13 p130 p137 port 14 p140 to p144, p146, p147 7 port 15 p150 to p153 4 serial array unit1 (4ch) uart3 iic20 rxd2/p14(rxd2/p76) txd2/p13(txd2/p77) rxd3/p143 txd3/p144 scl20/p15 sda20/p14 csi30 sck30/p142 so30/p144 si30/p143 csi31 sck31/p54 so31/p52 si31/p53 iic21 scl21/p70 sda21/p71 iic30 scl30/p142 sda30/p143 iic31 scl31/p54 sda31/p53 sck20/p15 so20/p13 si20/p14 csi20 sck21/p70 so21/p72 si21/p71 csi21 uart2 linsel timer array unit1 (4ch) ch2 ch3 ch0 ch1 ti12/to12/p66 ti13/to13/p67 ti11/to11/p65 ti10/to10/p64 serial interface iica1 sdaa1/p63 scla1/p62 real-time clock rl78 cpu core code flash memory data flash memory intp10/p76(intp10/p110), intp11/p77(intp11/p111) sck00/p10(sck00/p55) 2 crc low-speed on-chip oscillator 12-bit interval timer remark functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 46 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.5.13 100-pin products sck10/p04(sck10/p80) port 1 p10 to p17 port 2 p20 to p27 8 port 3 p30, p31 2 port 4 port 5 8 port 8 p40 to p47 8 p50 to p57 8 voltage regulator regc interrupt control ram window watchdog timer power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11(rxd0/p16) txd0/p12(txd0/p17) rxd1/p03(rxd1/p81) txd1/p02(txd1/p82) scl00/p10 sda00/p11 timer array unit0 (8ch) ch2 ti02/to02/p17 (ti02/to02/p15) ch3 ti03/to03/p31 (ti03/to03/p14) ch0 ch1 ch4 ti04/to04/p42 (ti04/to04/p13) ch5 ti05/to05/p46 (ti05/to05/p12) ch6 ti06/to06/p102 (ti06/to06/p11) ch7 intp8/p74(intp8/p86), intp9/p75(intp9/p87) 2 intp0/p137 intp3/p30(intp3/p57), intp4/p31(intp4/p146) intp6/p140(intp6/p84), intp7/p141(intp7/p85) intp1/p46(intp1/p56), intp2/p47 rxd2/p14 (rxd2/p76) csi10 so10/p02(so10/p82) si10/p03(si10/p81) a/d converter 8 ani0/p20 to ani7/p27 av refp /p20 av refm /p21 csi11 sck11/p30 so11/p51 si11/p50 iic01 scl01/p43 sda01/p44 iic10 scl10/p04(scl10/p80) sda10/p03(sda10/p81) iic11 scl11/p30 sda11/p50 ti07/to07/p145 (ti07/to07/p10) ti00/p00 to00/p01 bcd adjustment sck00/p10(sck00/p55) so00/p12(so00/p17) si00/p11(si00/p16) csi00 v ss , ev ss0 , ev ss1 toolrxd/p11, tooltxd/p12 v dd , ev dd0 , ev dd1 serial interface iica0 sdaa0/p61(sdaa0/p13) scla0/p60(scla0/p14) 2 2 2 intp5/p16(intp5/p12) multiplier& divider, mulitiply- accumulator xt1/p123 xt2/exclks/p124 port 0 p00 to p06 7 key return 8 kr0/p70 to kr7/p77 5 ani16/p03, ani17/p02, ani18/p147, ani19/p120, ani20/p100 sck01/p43 so01/p45 si01/p44 csi01 direct memory access control port 6 port 7 p70 to p77 8 p60 to p67 8 port 10 p100 to p102 3 buzzer output pclbuz0/p140 (pclbuz0/p31), pclbuz1/p141 (pclbuz1/p55) clock output control 2 ti01/to01/p16 rtc1hz/p30 rxd2/p14 (rxd2/p76) 7 ani8/p150 to ani14/p156 port 11 p110, p111 2 port 12 p121 to p124 4 p120 port 13 p130 p137 port 14 p140 to p147 8 port 15 p150 to p156 7 p80 to p87 8 serial array unit1 (4ch) uart3 iic20 rxd2/p14(rxd2/p76) txd2/p13(txd2/p77) rxd3/p143 txd3/p144 scl20/p15 sda20/p14 csi30 sck30/p142 so30/p144 si30/p143 csi31 sck31/p54 so31/p52 si31/p53 iic21 scl21/p70 sda21/p71 iic30 scl30/p142 sda30/p143 iic31 scl31/p54 sda31/p53 sck20/p15 so20/p13 si20/p14 csi20 sck21/p70 so21/p72 si21/p71 csi21 uart2 linsel timer array unit1 (4ch) ch2 ch3 ch0 ch1 ti12/to12/p66 ti13/to13/p67 ti11/to11/p65 ti10/to10/p64 serial interface iica1 sdaa1/p63 scla1/p62 real-time clock rl78 cpu core code flash memory data flash memory intp10/p76(intp10/p110), intp11/p77(intp11/p111) 2 crc low-speed on-chip oscillator 12-bit interval timer remark functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 47 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.5.14 128-pin products sck10/p04(sck10/p80) sck00/p10(sck00/p55) port 1 p10 to p17 port 2 p20 to p27 8 port 3 p30 to p37 8 port 4 port 5 8 port 8 p40 to p47 8 p50 to p57 8 voltage regulator regc interrupt control ram power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11(rxd0/p16) txd0/p12(txd0/p17) rxd1/p03(rxd1/p81) txd1/p02(txd1/p82) scl00/p10 sda00/p11 timer array unit0 (8ch) ch2 ti02/to02/p17 (ti02/to02/p15) ch3 ti03/to03/p31 (ti03/to03/p14) ch0 ch1 ch4 ti04/to04/p42 (ti04/to04/p13) ch5 ti05/to05/p46 (ti05/to05/p12) ch6 ti06/to06/p102 (ti06/to06/p11) ch7 intp8/p74 (intp8/p86), intp9/p75 (intp9/p87) 2 2 intp0/p137 intp3/p30 (intp3/p57), intp4/p31 (intp4/p146) intp6/p140 (intp6/p84), intp7/p141 (intp7/p85) intp1/p46 (intp1/p56), intp2/p47 rxd2/p14 (rxd2/p76) csi10 so10/p02(so10/p82) si10/p03(si10/p81) a/d converter 8 ani0/p20 to ani7/p27 av refp /p20 av refm /p21 port 9 csi11 sck11/p95 so11/p97 si11/p96 iic01 scl01/p43 sda01/p44 iic10 scl10/p04(scl10/p80) sda10/p03(sda10/p81) iic11 scl11/p95 sda11/p96 ti07/to07/p145 (ti07/to07/p10) ti00/p00 to00/p01 so00/p12(so00/p17) si00/p11(si00/p16) csi00 v ss , ev ss0 , ev ss1 toolrxd/p11, tooltxd/p12 v dd , ev dd0 , ev dd1 2 2 2 intp5/p16 (intp5/p12) xt1/p123 xt2/exclks/p124 port 0 p00 to p07 8 key return 8 kr0/p70 to kr7/p77 11 ani16/p03, ani17/p02, ani18/p147, ani19/p120, ani20/p100, ani21/37, ani22/p36, ani23/p35, ani24/p117, ani25/p116, ani26/p115 sck01/p43 so01/p45 si01/p44 csi01 port 6 port 7 p70 to p77 8 p60 to p67 8 port 10 p100 to p106 7 ti01/to01/p16 rxd2/p14 (rxd2/p76) 7 ani8/p150 to ani14/p156 port 11 p110 to p117 8 port 12 p121 to p124 4 p120, p125 to p127 port 13 p130 p137 port 14 p140 to p147 8 4 port 15 p150 to p156 7 p90 to p97 8 p80 to p87 8 serial array unit1 (4ch) uart3 iic20 rxd2/p14(rxd2/p76) txd2/p13(txd2/p77) rxd3/p143 txd3/p144 scl20/p15 sda20/p14 csi30 sck30/p142 so30/p144 si30/p143 csi31 sck31/p54 so31/p52 si31/p53 iic21 scl21/p70 sda21/p71 iic30 scl30/p142 sda30/p143 iic31 scl31/p54 sda31/p53 sck20/p15 so20/p13 si20/p14 csi20 sck21/p70 so21/p72 si21/p71 csi21 uart2 linsel timer array unit1 (8ch) ch2 ch3 ch0 ch1 ch4 ch5 ch6 ch7 ti12/to12/p66 ti13/to13/p67 ti14/to14/p103 ti15/to15/p104 ti16/to16/p105 ti17/to17/p106 ti11/to11/p65 ti10/to10/p64 window watchdog timer bcd adjustment serial interface iica0 sdaa0/p61(sdaa0/p13) scla0/p60(scla0/p14) multiplier& divider, mulitiply- accumulator buzzer output pclbuz0/p140 (pclbuz0/p31), pclbuz1/p141 (pclbuz1/p55) clock output control direct memory access control rtc1hz/p30 serial interface iica1 sdaa1/p63 scla1/p62 real-time clock rl78 cpu core code flash memory data flash memory 2 intp10/p76 (intp10/p110), intp11/p77 (intp11/p111) crc low-speed on-chip oscillator 12-bit interval timer remark functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). refer to figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g13 user?s manual.
rl78/g13 1. outline page 48 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 1.6 outline of functions [20-pin, 24-pin, 25-pin, 30-pi n, 32-pin, 36-pin products] caution this outline describes the functi ons at the time when periphera l i/o redirection register (pior) is set to 00h. (1/2) 20-pin 24-pin 25-pin 30-pin 32-pin 36-pin item r5f1006x r5f1016x r5f1007x r5f1017x r5f1008x r5f1018x r5f100ax r5f101ax r5f100bx r5f101bx r5f100cx r5f101cx code flash memory (kb) 16 to 64 16 to 64 16 to 64 16 to 128 16 to 128 16 to 128 data flash memory (kb) 4 ? 4 ? 4 ? 4 to 8 ? 4 to 8 ? 4 to 8 ? ram (kb) 2 to 4 note1 2 to 4 note1 2 to 4 note1 2 to 12 note1 2 to 12 note1 2 to 12 note1 address space 1 mb high-speed system clock x1 (crystal/ceramic) oscillation, extern al main system clock input (exclk) hs (high-speed main) mode: 1 to 20 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) main system clock high-speed on-chip oscillator hs (high-speed main) mode: 1 to 32 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) subsystem clock ? low-speed on-chip oscillator 15 khz (typ.) general-purpose registers (8-bit register ? 8) ? 4 banks 0.03125 ? s (high-speed on-chip oscillator: f ih = 32 mhz operation) minimum instruction execution time 0.05 ? s (high-speed system clock: f mx = 20 mhz operation) instruction set ? data transfer (8/16 bits) ? adder and subtractor/logical operation (8/16 bits) ? multiplication (8 bits ? 8 bits) ? rotate, barrel shift, and bit manipulation (set, reset, test, and boolean operation), etc. i/o port total 16 20 21 26 28 32 cmos i/o 13 (n-ch o.d. i/o [v dd withstand voltage]: 5) 15 (n-ch o.d. i/o [v dd withstand voltage]: 6) 15 (n-ch o.d. i/o [v dd withstand voltage]: 6) 21 (n-ch o.d. i/o [v dd withstand voltage]: 9) 22 (n-ch o.d. i/o [v dd withstand voltage]: 9) 26 (n-ch o.d. i/o [v dd withstand voltage]: 10) cmos input 3 3 3 3 3 3 cmos output ? ? 1 ? ? ? n-ch o.d. i/o (withstand voltage: 6 v) ? 2 2 2 3 3 16-bit timer 8 channels watchdog timer 1 channel timer real-time clock (rtc) 1 channel note 2 12-bit interval timer (it) 1 channel timer output 3 channels (pwm outputs: 2 note 3 ) 4 channels (pwm outputs: 3 note 3 ) 4 channels (pwm outputs: 3 note 3 ), 8 channels (pwm outputs: 7 note 3 ) note 4 rtc output ? notes 1. the flash library uses ram in self-progra mming and rewriting of the data flash memory. the target products and start address of the ram areas used by the flash library are shown below. r5f100xd, r5f101xd (x = 6 to 8, a to c): start address ff300h r5f100xe, r5f101xe (x = 6 to 8, a to c): start address fef00h for the ram areas used by the flash library, see self ram list of flash self-programming library for rl78 family (r20ut2944) . 2. only the constant-period interrupt function when the low-speed on-chip oscillator clock (f il ) is selected
rl78/g13 1. outline page 49 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 3. the number of pwm outputs varies depending on the setting of channels in use (the number of masters and slaves) (see 6.9.3 operation as multiple pwm output function in the rl78/g13 user?s manual). 4. when setting to pior = 1 (2/2) 20-pin 24-pin 25-pin 30-pin 32-pin 36-pin item r5f1006x r5f1016x r5f1007x r5f1017x r5f1008x r5f1018x r5f100ax r5f101ax r5f100bx r5f101bx r5f100cx r5f101cx ? 1 1 2 2 2 clock output/buzzer output ? 2.44 khz, 4.88 khz, 9.76 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (main system clock: f main = 20 mhz operation) 8/10-bit resolution a/d converter 6 channels 6 c hannels 6 channels 8 channels 8 channels 8 channels serial interface [20-pin, 24-pin, 25-pin products] ? csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel ? csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel [30-pin, 32-pin products] ? csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel ? csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel ? csi: 1 channel/simplified i 2 c: 1 channel/uart (uart supporting lin-bus): 1 channel [36-pin products] ? csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel ? csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel ? csi: 2 channels/simplified i 2 c: 2 channels/uart (uart supporting lin-bus): 1 channel i 2 c bus ? 1 channel 1 channel 1 chann el 1 channel 1 channel multiplier and divider/multiply- accumulator ? 16 bits ? 16 bits = 32 bits (unsigned or signed) ? 32 bits ? 32 bits = 32 bits (unsigned) ? 16 bits ? 16 bits + 32 bits = 32 bits (unsigned or signed) dma controller 2 channels internal 23 24 24 27 27 27 vectored interrupt sources external 3 5 5 6 6 6 key interrupt ? reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-reset ? internal reset by voltage detector ? internal reset by illegal instruction execution note ? internal reset by ram parity error ? internal reset by illegal-memory access power-on-reset circuit ? power-on-reset: 1.51 v (typ.) ? power-down-reset: 1.50 v (typ.) voltage detector ? rising edge : 1.67 v to 4.06 v (14 stages) ? falling edge : 1.63 v to 3.98 v (14 stages) on-chip debug function provided power supply voltage v dd = 1.6 to 5.5 v (t a = -40 to +85c) v dd = 2.4 to 5.5 v (t a = -40 to +105c) operating ambient temperature t a = 40 to +85c (a: consumer applic ations, d: industrial applications ) t a = 40 to +105c (g: industrial applications) note the illegal instruction is generated when instruction code ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator.
rl78/g13 1. outline page 50 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 [40-pin, 44-pin, 48-pin, 52-pin, 64-pin products] caution this outline describes the functi ons at the time when periphera l i/o redirection register (pior) is set to 00h. (1/2) 40-pin 44-pin 48-pin 52-pin 64-pin item r5f100ex r5f101ex r5f100fx r5f101fx r5f100gx r5f101gx r5f100jx r5f101jx r5f100lx r5f101lx code flash memory (kb) 16 to 192 16 to 512 16 to 512 32 to 512 32 to 512 data flash memory (kb) 4 to 8 ? 4 to 8 ? 4 to 8 ? 4 to 8 ? 4 to 8 ? ram (kb) 2 to 16 note1 2 to 32 note1 2 to 32 note1 2 to 32 note1 2 to 32 note1 address space 1 mb high-speed system clock x1 (crystal/ceramic) oscillation, extern al main system clock input (exclk) hs (high-speed main) mode: 1 to 20 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) main system clock high-speed on-chip oscillator hs (high-speed main) mode: 1 to 32 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) subsystem clock xt1 (crystal) oscillation, external subsystem clock input (exclks) 32.768 khz low-speed on-chip oscillator 15 khz (typ.) general-purpose registers (8-bit register ? 8) ? 4 banks 0.03125 ? s (high-speed on-chip oscillator: f ih = 32 mhz operation) 0.05 ? s (high-speed system clock: f mx = 20 mhz operation) minimum instruction execution time 30.5 ? s (subsystem clock: f sub = 32.768 khz operation) instruction set ? data transfer (8/16 bits) ? adder and subtractor/logical operation (8/16 bits) ? multiplication (8 bits ? 8 bits) ? rotate, barrel shift, and bit manipulation (set, reset, test, and boolean operation), etc. i/o port total 36 40 44 48 58 cmos i/o 28 (n-ch o.d. i/o [v dd withstand voltage]: 10) 31 (n-ch o.d. i/o [v dd withstand voltage]: 10) 34 (n-ch o.d. i/o [v dd withstand voltage]: 11) 38 (n-ch o.d. i/o [v dd withstand voltage]: 13) 48 (n-ch o.d. i/o [v dd withstand voltage]: 15) cmos input 5 5 5 5 5 cmos output ? ? 1 1 1 n-ch o.d. i/o (withstand voltage: 6 v) 3 4 4 4 4 16-bit timer 8 channels watchdog timer 1 channel timer real-time clock (rtc) 1 channel 12-bit interval timer (it) 1 channel timer output 4 channels (pwm outputs: 3 note 2 ), 8 channels (pwm outputs: 7 note 2 ) note 3 5 channels (pwm outputs: 4 note 2 ), 8 channels (pwm outputs: 7 note 2 ) note 3 8 channels (pwm outputs: 7 note 2 ) rtc output 1 channel ? 1 hz (subsystem clock: f sub = 32.768 khz) notes 1. the flash library uses ram in self-progra mming and rewriting of the data flash memory. the target products and start address of the ram areas used by the flash library are shown below. r5f100xd, r5f101xd (x = e to g, j, l): start address ff300h r5f100xe, r5f101xe (x = e to g, j, l): start address fef00h r5f100xj, r5f101xj (x = f, g, j, l): start address faf00h r5f100xl, r5f101xl (x = f, g, j, l): start address f7f00h for the ram areas used by the flash library, see self ram list of flash self-programming library for rl78 family (r20ut2944) .
rl78/g13 1. outline page 51 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 2. the number of pwm outputs varies depending on the setting of channels in use (the number of masters and slaves) (see 6.9.3 operation as multiple pwm output function in the rl78/g13 user?s manual). 3. when setting to pior = 1 (2/2) 40-pin 44-pin 48-pin 52-pin 64-pin item r5f100ex r5f101ex r5f100fx r5f101fx r5f100gx r5f101gx r5f100jx r5f101jx r5f100lx r5f101lx 2 2 2 2 2 clock output/buzzer output ? 2.44 khz, 4.88 khz, 9.76 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (main system clock: f main = 20 mhz operation) ? 256 hz, 512 hz, 1.024 khz, 2.048 khz, 4.096 khz, 8.192 khz, 16.384 khz, 32.768 khz (subsystem clock: f sub = 32.768 khz operation) 8/10-bit resolution a/d converter 9 channel s 10 channels 10 channels 12 channels 12 channels serial interface [40-pin, 44-pin products] ? csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel ? csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel ? csi: 2 channels/simplified i 2 c: 2 channels/uart (uart supporting lin-bus): 1 channel [48-pin, 52-pin products] ? csi: 2 channels/simplified i 2 c: 2 channels/uart: 1 channel ? csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel ? csi: 2 channels/simplified i 2 c: 2 channels/uart (uart supporting lin-bus): 1 channel [64-pin products] ? csi: 2 channels/simplified i 2 c: 2 channels/uart: 1 channel ? csi: 2 channels/simplified i 2 c: 2 channels/uart: 1 channel ? csi: 2 channels/simplified i 2 c: 2 channels/uart (uart supporting lin-bus): 1 channel i 2 c bus 1 channel 1 channel 1 channel 1 channel 1 channel multiplier and divider/multiply- accumulator ? 16 bits ? 16 bits = 32 bits (unsigned or signed) ? 32 bits ? 32 bits = 32 bits (unsigned) ? 16 bits ? 16 bits + 32 bits = 32 bits (unsigned or signed) dma controller 2 channels internal 27 27 27 27 27 vectored interrupt sources external 7 7 10 12 13 key interrupt 4 4 6 8 8 reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-reset ? internal reset by voltage detector ? internal reset by illegal instruction execution note ? internal reset by ram parity error ? internal reset by illegal-memory access power-on-reset circuit ? power-on-reset: 1.51 v (typ.) ? power-down-reset: 1.50 v (typ.) voltage detector ? rising edge : 1.67 v to 4.06 v (14 stages) ? falling edge : 1.63 v to 3.98 v (14 stages) on-chip debug function provided power supply voltage v dd = 1.6 to 5.5 v (t a = -40 to +85c) v dd = 2.4 to 5.5 v (t a = -40 to +105c) operating ambient temperature t a = 40 to +85c (a: consumer applic ations, d: industrial applications) t a = 40 to +105c (g: industrial applications) note the illegal instruction is generated wh en instruction code ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator.
rl78/g13 1. outline page 52 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 [80-pin, 100-pin, 128-pin products] caution this outline describes the functi ons at the time when periphera l i/o redirection register (pior) is set to 00h. (1/2) 80-pin 100-pin 128-pin item r5f100mx r5f101mx r5f100px r5f101px r5f100sx r5f101sx code flash memory (kb) 96 to 512 96 to 512 192 to 512 data flash memory (kb) 8 ? 8 ? 8 ? ram (kb) 8 to 32 note 1 8 to 32 note 1 16 to 32 note 1 address space 1 mb high-speed system clock x1 (crystal/ceramic) oscillation, extern al main system clock input (exclk) hs (high-speed main) mode: 1 to 20 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) main system clock high-speed on-chip oscillator hs (high-speed main) mode: 1 to 32 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) subsystem clock xt1 (crystal) oscillation, external subsystem clock input (exclks) 32.768 khz low-speed on-chip oscillator 15 khz (typ.) general-purpose register (8-bit register ? 8) ? 4 banks 0.03125 ? s (high-speed on-chip oscillator: f ih = 32 mhz operation) 0.05 ? s (high-speed system clock: f mx = 20 mhz operation) minimum instruction execution time 30.5 ? s (subsystem clock: f sub = 32.768 khz operation) instruction set ? data transfer (8/16 bits) ? adder and subtractor/logical operation (8/16 bits) ? multiplication (8 bits ? 8 bits) ? rotate, barrel shift, and bit manipulation (set, reset, test, and boolean operation), etc. i/o port total 74 92 120 cmos i/o 64 (n-ch o.d. i/o [ev dd withstand voltage]: 21) 82 (n-ch o.d. i/o [ev dd withstand voltage]: 24) 110 (n-ch o.d. i/o [ev dd withstand voltage]: 25) cmos input 5 5 5 cmos output 1 1 1 n-ch o.d. i/o (withstand voltage: 6 v) 4 4 4 16-bit timer 12 channels 12 channels 16 channels watchdog timer 1 channel 1 channel 1 channel timer real-time clock (rtc) 1 channel 1 channel 1 channel 12-bit interval timer (it) 1 channel 1 channel 1 channel timer output 12 channels (pwm outputs: 10 note 2 ) 12 channels (pwm outputs: 10 note 2 ) 16 channels (pwm outputs: 14 note 2 ) rtc output 1 channel ? 1 hz (subsystem clock: f sub = 32.768 khz) notes 1. the flash library uses ram in self-progra mming and rewriting of the data flash memory. the target products and start address of the ram areas used by the flash library are shown below. r5f100xj, r5f101xj (x = m, p): start address faf00h r5f100xl, r5f101xl (x = m, p, s): start address f7f00h for the ram areas used by the flash library, see self ram list of flash self-programming library for rl78 family (r20ut2944) .
rl78/g13 1. outline page 53 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 2. the number of pwm outputs varies depending on the setting of channels in use (the number of masters and slaves) (see 6.9.3 operation as multiple pwm output function in the rl78/g13 user?s manual). (2/2) 80-pin 100-pin 128-pin item r5f100mx r5f101mx r5f100px r5f101px r5f100sx r5f101sx 2 2 2 clock output/buzzer output ? 2.44 khz, 4.88 khz, 9.76 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (main system clock: f main = 20 mhz operation) ? 256 hz, 512 hz, 1.024 khz, 2.048 khz, 4.096 khz, 8.192 khz, 16.384 khz, 32.768 khz (subsystem clock: f sub = 32.768 khz operation) 8/10-bit resolution a/d converter 17 channels 20 channels 26 channels serial interface [80-pin, 100-pin, 128-pin products] ? csi: 2 channels/simplified i 2 c: 2 channels/uart: 1 channel ? csi: 2 channels/simplified i 2 c: 2 channels/uart: 1 channel ? csi: 2 channels/simplified i 2 c: 2 channels/uart (uart supporting lin-bus): 1 channel ? csi: 2 channels/simplified i 2 c: 2 channels/uart: 1 channel i 2 c bus 2 channels 2 channels 2 channels multiplier and divider/multiply- accumulator ? 16 bits ? 16 bits = 32 bits (unsigned or signed) ? 32 bits ? 32 bits = 32 bits (unsigned) ? 16 bits ? 16 bits + 32 bits = 32 bits (unsigned or signed) dma controller 4 channels internal 37 37 41 vectored interrupt sources external 13 13 13 key interrupt 8 8 8 reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-reset ? internal reset by voltage detector ? internal reset by illegal instruction execution note ? internal reset by ram parity error ? internal reset by illegal-memory access power-on-reset circuit ? power-on-reset: 1.51 v (typ.) ? power-down-reset: 1.50 v (typ.) voltage detector ? rising edge : 1.67 v to 4.06 v (14 stages) ? falling edge : 1.63 v to 3.98 v (14 stages) on-chip debug function provided power supply voltage v dd = 1.6 to 5.5 v (t a = -40 to +85c) v dd = 2.4 to 5.5 v (t a = -40 to +105c) operating ambient temperature t a = 40 to +85c (a: consumer applic ations, d: industrial applications ) t a = 40 to +105c (g: industrial applications) note the illegal instruction is generated wh en instruction code ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator.
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 54 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 2. electrical specifications (t a = -40 to +85 ?c) this chapter describes the following electrical specifications. target products a: consumer applications t a = ? 40 to +85c r5f100xxaxx, r5f101xxaxx d: industrial applications t a = ? 40 to +85c r5f100xxdxx, r5f101xxdxx g: industrial applications when t a = ? 40 to +105c products is used in the range of t a = ? 40 to +85c r5f100xxgxx cautions 1. the rl78 microcontrollers have an on- chip debug func tion, which is provided for development and evaluation. do not use the on-chip debug func tion in products designated for mass production, because the gua ranteed number of rewritable times of the flash memory may be exceeded when this func tion is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. 2. with products not provided with an ev dd0 , ev dd1 , ev ss0 , or ev ss1 pin, replace ev dd0 and ev dd1 with v dd , or replace ev ss0 and ev ss1 with v ss . 3. the pins mounted depend on the product. refer to 2.1 port function to 2.2.1 functions for each product.
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 55 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 2.1 absolute maximum ratings absolute maximum ratings (t a = 25 ? c) (1/2) parameter symbols conditions ratings unit v dd ?0.5 to +6.5 v ev dd0 , ev dd1 ev dd0 = ev dd1 ?0.5 to +6.5 v supply voltage ev ss0 , ev ss1 ev ss0 = ev ss1 ?0.5 to +0.3 v regc pin input voltage v iregc regc ?0.3 to +2.8 and ?0.3 to v dd +0.3 note 1 v v i1 p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p140 to p147 ?0.3 to ev dd0 +0.3 and ?0.3 to v dd +0.3 note 2 v v i2 p60 to p63 (n-ch open-drain) ?0.3 to +6.5 v input voltage v i3 p20 to p27, p121 to p124, p137, p150 to p156, exclk, exclks, reset ?0.3 to v dd +0.3 note 2 v v o1 p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p130, p140 to p147 ?0.3 to ev dd0 +0.3 and ?0.3 to v dd +0.3 note 2 v output voltage v o2 p20 to p27, p150 to p156 ?0.3 to v dd +0.3 note 2 v v ai1 ani16 to ani26 ?0.3 to ev dd0 +0.3 and ?0.3 to av ref (+) +0.3 notes 2, 3 v analog input voltage v ai2 ani0 to ani14 ?0.3 to v dd +0.3 and ?0.3 to av ref (+) +0.3 notes 2, 3 v notes 1. connect the regc pin to vss via a capacitor (0.47 to 1 ? f). this value regulates the absolute maximum rating of the regc pin. do not use this pin with voltage applied to it. 2. must be 6.5 v or lower. 3. do not exceed av ref (+) + 0.3 v in case of a/d conversion target pin . caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefor e the product must be used under conditions that ensure that the absolute maximum rati ngs are not exceeded. remarks 1. unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins. 2. av ref (+) : + side reference voltage of the a/d converter. 3. v ss : reference voltage
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 56 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 absolute maximum ratings (t a = 25 ? c) (2/2) parameter symbols conditions ratings unit per pin p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p130, p140 to p147 ?40 ma p00 to p04, p07, p32 to p37, p40 to p47, p102 to p106, p120, p125 to p127, p130, p140 to p145 ?70 ma i oh1 total of all pins ?170 ma p05, p06, p10 to p17, p30, p31, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100, p101, p110 to p117, p146, p147 ?100 ma per pin ?0.5 ma output current, high i oh2 total of all pins p20 to p27, p150 to p156 ?2 ma per pin p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p130, p140 to p147 40 ma p00 to p04, p07, p32 to p37, p40 to p47, p102 to p106, p120, p125 to p127, p130, p140 to p145 70 ma i ol1 total of all pins 170 ma p05, p06, p10 to p17, p30, p31, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, p100, p101, p110 to p117, p146, p147 100 ma per pin 1 ma output current, low i ol2 total of all pins p20 to p27, p150 to p156 5 ma in normal operation mode operating ambient temperature t a in flash memory programming mode ?40 to +85 ? c storage temperature t stg ?65 to +150 ? c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefor e the product must be used under conditions that ensure that the absolute maximum rati ngs are not exceeded. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 57 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 2.2 oscillator characteristics 2.2.1 x1, xt1 oscillator characteristics (t a = ? 40 to +85 ? c, 1.6 v ? v dd ? 5.5 v, v ss = 0 v) parameter resonator conditions min. typ. max. unit 2.7 v ? v dd ? 5.5 v 1.0 20.0 mhz 2.4 v ? v dd ? 2.7 v 1.0 16.0 mhz 1.8 v ? v dd ? 2.4 v 1.0 8.0 mhz x1 clock oscillation frequency (f x ) note ceramic resonator/ crystal resonator 1.6 v ? v dd ? 1.8 v 1.0 4.0 mhz xt1 clock oscillation frequency (f x ) note crystal resonator 32 32.768 35 khz note indicates only permissible oscillator frequency ranges. re fer to ac characteristics for instruction execution time. request evaluation by the manufacturer of t he oscillator circuit mounted on a board to check the oscillator characteristics. caution since the cpu is started by the high-speed on-chip oscillator cl ock after a reset release, check the x1 clock oscillation stabilization time using th e oscillation stabilization time counter status register (ostc) by the user. dete rmine the oscillation stabilization time of the ostc register and the oscillation stabilization time select register (osts) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. remark when using the x1 oscillator and xt1 oscillator, refer to 5.4 system clock oscillator. 2.2.2 on-chip oscillator characteristics (t a = ? 40 to +85 ? c, 1.6 v ? v dd ? 5.5 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit high-speed on-chip oscillator clock frequency notes 1, 2 f ih 1 32 mhz 1.8 v ? v dd ? 5.5 v ? 1.0 +1.0 % ?20 to +85 ? c 1.6 v ? v dd < 1.8 v ? 5.0 +5.0 % 1.8 v ? v dd ? 5.5 v ? 1.5 +1.5 % high-speed on-chip oscillator clock frequency accuracy ?40 to ?20 ? c 1.6 v ? v dd < 1.8 v ? 5.5 +5.5 % low-speed on-chip oscillator clock frequency f il 15 khz low-speed on-chip oscillator clock frequency accuracy ? 15 +15 % notes 1. high-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000c2h/010c2h) and bits 0 to 2 of hocodiv register. 2. this indicates the oscillator characteristics only. refer to ac characteristics for instruction execution time.
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 58 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 2.3 dc characteristics 2.3.1 pin characteristics (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (1/5) items symbol conditions min. typ. max. unit per pin for p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p130, p140 to p147 1.6 v ? ev dd0 ? 5.5 v ?10.0 note 2 ma 4.0 v ? ev dd0 ? 5.5 v ? 55.0 ma 2.7 v ? ev dd0 < 4.0 v ? 10.0 ma 1.8 v ? ev dd0 < 2.7 v ?5.0 ma total of p00 to p04, p07, p32 to p37, p40 to p47, p102 to p106, p120, p125 to p127, p130, p140 to p145 (when duty ? 70% note 3 ) 1.6 v ? ev dd0 < 1.8 v ?2.5 ma 4.0 v ? ev dd0 ? 5.5 v ? 80.0 ma 2.7 v ? ev dd0 < 4.0 v ? 19.0 ma 1.8 v ? ev dd0 < 2.7 v ? 10.0 ma total of p05, p06, p10 to p17, p30, p31, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100, p101, p110 to p117, p146, p147 (when duty ? 70% note 3 ) 1.6 v ? ev dd0 < 1.8 v ?5.0 ma i oh1 total of all pins (when duty ? 70% note 3 ) 1.6 v ? ev dd0 ? 5.5 v ?135.0 note 4 ma per pin for p20 to p27, p150 to p156 1.6 v ? v dd ? 5.5 v ?0.1 note 2 ma output current, high note 1 i oh2 total of all pins (when duty ? 70% note 3 ) 1.6 v ? v dd ? 5.5 v ?1.5 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from the ev dd0 , ev dd1 , v dd pins to an output pin. 2. however, do not exceed the total current value. 3. specification under conditions where the duty factor ? 70%. the output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changi ng the duty factor from 70% to n%). ? total output current of pins = (i oh 0.7)/(n 0.01) where n = 80% and i oh = ? 10.0 ma total output current of pins = ( ? 10.0 0.7)/(80 0.01) ? ? 8.7 ma however, the current that is allowed to flow into one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. 4. the applied current for the products for indus trial application (r5f100xxdxx, r5f101xxdxx, r5f100xxgxx) is ? 100 ma. caution p00, p02 to p04, p 10 to p15, p17, p43 to p45, p50, p52 to p55, p71, p74, p80 to p82, p96, and p142 to p144 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 59 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/5) items symbol conditions min. typ. max. unit per pin for p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p130, p140 to p147 20.0 note 2 ma per pin for p60 to p63 15.0 note 2 ma 4.0 v ? ev dd0 ? 5.5 v 70.0 ma 2.7 v ? ev dd0 < 4.0 v 15.0 ma 1.8 v ? ev dd0 < 2.7 v 9.0 ma total of p00 to p04, p07, p32 to p37, p40 to p47, p102 to p106, p120, p125 to p127, p130, p140 to p145 (when duty ? 70% note 3 ) 1.6 v ? ev dd0 < 1.8 v 4.5 ma 4.0 v ? ev dd0 ? 5.5 v 80.0 ma 2.7 v ? ev dd0 < 4.0 v 35.0 ma 1.8 v ? ev dd0 < 2.7 v 20.0 ma total of p05, p06, p10 to p17, p30, p31, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, p100, p101, p110 to p117, p146, p147 (when duty ? 70% note 3 ) 1.6 v ? ev dd0 < 1.8 v 10.0 ma i ol1 total of all pins (when duty ? 70% note 3 ) 150.0 ma per pin for p20 to p27, p150 to p156 0.4 note 2 ma output current, low note 1 i ol2 total of all pins (when duty ? 70% note 3 ) 1.6 v ? v dd ? 5.5 v 5.0 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from an output pin to the ev ss0 , ev ss1 and v ss pin. 2. however, do not exceed the total current value. 3. specification under conditions where the duty factor ? 70%. the output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changi ng the duty factor from 70% to n%). ? total output current of pins = (i ol 0.7)/(n 0.01) where n = 80% and i ol = 10.0 ma total output current of pi ns = (10.0 0.7)/(80 0.01) ? 8.7 ma however, the current that is allowed to flow into one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 60 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (3/5) items symbol conditions min. typ. max. unit v ih1 p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p140 to p147 normal input buffer 0.8ev dd0 ev dd0 v ttl input buffer 4.0 v ? ev dd0 ? 5.5 v 2.2 ev dd0 v ttl input buffer 3.3 v ? ev dd0 ? 4.0 v 2.0 ev dd0 v v ih2 p01, p03, p04, p10, p11, p13 to p17, p43, p44, p53 to p55, p80, p81, p142, p143 ttl input buffer 1.6 v ? ev dd0 ? 3.3 v 1.5 ev dd0 v v ih3 p20 to p27, p150 to p156 0.7v dd v dd v v ih4 p60 to p63 0.7ev dd0 6.0 v input voltage, high v ih5 p121 to p124, p137, exclk, exclks, reset 0.8v dd v dd v v il1 p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p140 to p147 normal input buffer 0 0.2ev dd0 v ttl input buffer 4.0 v ? ev dd0 ? 5.5 v 0 0.8 v ttl input buffer 3.3 v ? ev dd0 ? 4.0 v 0 0.5 v v il2 p01, p03, p04, p10, p11, p13 to p17, p43, p44, p53 to p55, p80, p81, p142, p143 ttl input buffer 1.6 v ? ev dd0 ? 3.3 v 0 0.32 v v il3 p20 to p27, p150 to p156 0 0.3v dd v v il4 p60 to p63 0 0.3ev dd0 v input voltage, low v il5 p121 to p124, p137, exclk, exclks, reset 0 0.2v dd v caution the maximum value of v ih of pins p00, p02 to p04, p10 to p15, p17, p43 to p45, p50, p52 to p55, p71, p74, p80 to p82, p96, and p142 to p144 is ev dd0 , even in the n-ch open-drain mode. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 61 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (4/5) items symbol conditions min. typ. max. unit 4.0 v ? ev dd0 ? 5.5 v, i oh1 = ? 10.0 ma ev dd0 ? 1.5 v 4.0 v ? ev dd0 ? 5.5 v, i oh1 = ? 3.0 ma ev dd0 ? 0.7 v 2.7 v ? ev dd0 ? 5.5 v, i oh1 = ? 2.0 ma ev dd0 ? 0.6 v 1.8 v ? ev dd0 ? 5.5 v, i oh1 = ? 1.5 ma ev dd0 ? 0.5 v v oh1 p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p130, p140 to p147 1.6 v ? ev dd0 < 5.5 v, i oh1 = ? 1.0 ma ev dd0 ? 0.5 v output voltage, high v oh2 p20 to p27, p150 to p156 1.6 v ? v dd ? 5.5 v, i oh2 = ?100 ? a v dd ? 0.5 v 4.0 v ? ev dd0 ? 5.5 v, i ol1 = 20 ma 1.3 v 4.0 v ? ev dd0 ? 5.5 v, i ol1 = 8.5 ma 0.7 v 2.7 v ? ev dd0 ? 5.5 v, i ol1 = 3.0 ma 0.6 v 2.7 v ? ev dd0 ? 5.5 v, i ol1 = 1.5 ma 0.4 v 1.8 v ? ev dd0 ? 5.5 v, i ol1 = 0.6 ma 0.4 v v ol1 p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p130, p140 to p147 1.6 v ? ev dd0 < 5.5 v, i ol1 = 0.3 ma 0.4 v v ol2 p20 to p27, p150 to p156 1.6 v ? v dd ? 5.5 v, i ol2 = 400 ? a 0.4 v 4.0 v ? ev dd0 ? 5.5 v, i ol3 = 15.0 ma 2.0 v 4.0 v ? ev dd0 ? 5.5 v, i ol3 = 5.0 ma 0.4 v 2.7 v ? ev dd0 ? 5.5 v, i ol3 = 3.0 ma 0.4 v 1.8 v ? ev dd0 ? 5.5 v, i ol3 = 2.0 ma 0.4 v output voltage, low v ol3 p60 to p63 1.6 v ? ev dd0 < 5.5 v, i ol3 = 1.0 ma 0.4 v caution p00, p02 to p04, p 10 to p15, p17, p43 to p45, p50, p52 to p55, p71, p74, p80 to p82, p96, and p142 to p144 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 62 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (5/5) items symbol conditions min. typ. max. unit i lih1 p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p140 to p147 v i = ev dd0 1 ? a i lih2 p20 to p27, p137, p150 to p156, reset v i = v dd 1 ? a in input port or external clock input 1 ? a input leakage current, high i lih3 p121 to p124 (x1, x2, xt1, xt2, exclk, exclks) v i = v dd in resonator connection 10 ? a i lil1 p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p140 to p147 v i = ev ss0 ?1 ? a i lil2 p20 to p27, p137, p150 to p156, reset v i = v ss ?1 ? a in input port or external clock input ?1 ? a input leakage current, low i lil3 p121 to p124 (x1, x2, xt1, xt2, exclk, exclks) v i = v ss in resonator connection ?10 ? a on-chip pll-up resistance r u p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p140 to p147 v i = ev ss0 , in input port 10 20 100 k ? remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 63 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 2.3.2 supply current characteristics (1) flash rom: 16 to 64 kb of 20- to 64-pin products (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 ? v dd ? 5.5 v, v ss = ev ss0 = 0 v) (1/2) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 2.1 ma basic operation v dd = 3.0 v 2.1 ma v dd = 5.0 v 4.6 7.0 ma f ih = 32 mhz note 3 normal operation v dd = 3.0 v 4.6 7.0 ma v dd = 5.0 v 3.7 5.5 ma ? f ih = 24 mhz note 3 normal operation v dd = 3.0 v 3.7 5.5 ma v dd = 5.0 v 2.7 4.0 ma ? hs (high- speed main) mode note 5 f ih = 16 mhz note 3 normal operation v dd = 3.0 v 2.7 4.0 ma v dd = 3.0 v 1.2 1.8 ma ? ls (low- speed main) mode note 5 f ih = 8 mhz note 3 normal operation v dd = 2.0 v 1.2 1.8 ma v dd = 3.0 v 1.2 1.7 ma ? lv ( low- voltage main) mode note 5 f ih = 4 mhz note 3 normal operation v dd = 2.0 v 1.2 1.7 ma square wave input 3.0 4.6 ma f mx = 20 mhz note 2 , v dd = 5.0 v normal operation resonator connection 3.2 4.8 ma square wave input 3.0 4.6 ma ? f mx = 20 mhz note 2 , v dd = 3.0 v normal operation resonator connection 3.2 4.8 ma square wave input 1.9 2.7 ma ? f mx = 10 mhz note 2 , v dd = 5.0 v normal operation resonator connection 1.9 2.7 ma square wave input 1.9 2.7 ma ? hs (high- speed main) mode note 5 f mx = 10 mhz note 2 , v dd = 3.0 v normal operation resonator connection 1.9 2.7 ma square wave input 1.1 1.7 ma ? f mx = 8 mhz note 2 , v dd = 3.0 v normal operation resonator connection 1.1 1.7 ma square wave input 1.1 1.7 ma ? ls (low- speed main) mode note 5 f mx = 8 mhz note 2 , v dd = 2.0 v normal operation resonator connection 1.1 1.7 ma square wave input 4.1 4.9 ? a f sub = 32.768 khz note 4 t a = ?40 ? c normal operation resonator connection 4.2 5.0 ? a square wave input 4.1 4.9 ? a f sub = 32.768 khz note 4 t a = +25 ? c normal operation resonator connection 4.2 5.0 ? a square wave input 4.2 5.5 ? a f sub = 32.768 khz note 4 t a = +50 ? c normal operation resonator connection 4.3 5.6 ? a square wave input 4.3 6.3 ? a f sub = 32.768 khz note 4 t a = +70 ? c normal operation resonator connection 4.4 6.4 ? a square wave input 4.6 7.7 ? a supply current note 1 i dd1 operating mode subsystem clock operation f sub = 32.768 khz note 4 t a = +85 ? c normal operation resonator connection 4.7 7.8 ? a (notes and remarks are listed on the next page.)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 64 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 notes 1. total current flowing into v dd and ev dd0 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 or v ss , ev ss0 . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d conver ter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the cu rrent flowing during data flash rewrite. 2. when high-speed on-chip oscillator and subsystem clock are stopped. 3. when high-speed system clock and subsystem clock are stopped. 4. when high-speed on-chip oscillator and high-spee d system clock are stopped. when amphs1 = 1 (ultra-low power consumption oscillation). however, not including the current flowing into the rtc, 12- bit interval timer, and watchdog timer. 5. relationship between operation voltage width, oper ation frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v ? v dd ? 5.5 v@1 mhz to 32 mhz 2.4 v ? v dd ? 5.5 v@1 mhz to 16 mhz ls (low-speed main) mode: 1.8 v ? v dd ? 5.5 v@1 mhz to 8 mhz lv (low-voltage main) mode: 1.6 v ? v dd ? 5.5 v@1 mhz to 4 mhz remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation, temper ature condition of t he typ. value is t a = 25 ?c
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 65 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (1) flash rom: 16 to 64 kb of 20- to 64-pin products (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 ? v dd ? 5.5 v, v ss = ev ss0 = 0 v) (2/2) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 0.54 1.63 ma f ih = 32 mhz note 4 v dd = 3.0 v 0.54 1.63 ma v dd = 5.0 v 0.44 1.28 ma f ih = 24 mhz note 4 v dd = 3.0 v 0.44 1.28 ma v dd = 5.0 v 0.40 1.00 ma hs (high- speed main) mode note 7 f ih = 16 mhz note 4 v dd = 3.0 v 0.40 1.00 ma v dd = 3.0 v 260 530 ? a ls (low- speed main) mode note 7 f ih = 8 mhz note 4 v dd = 2.0 v 260 530 ? a v dd = 3.0 v 420 640 ? a lv ( low- voltage main) mode note 7 f ih = 4 mhz note 4 v dd = 2.0 v 420 640 ? a square wave input 0.28 1.00 ma f mx = 20 mhz note 3 , v dd = 5.0 v resonator connection 0.45 1.17 ma square wave input 0.28 1.00 ma f mx = 20 mhz note 3 , v dd = 3.0 v resonator connection 0.45 1.17 ma square wave input 0.19 0.60 ma f mx = 10 mhz note 3 , v dd = 5.0 v resonator connection 0.26 0.67 ma square wave input 0.19 0.60 ma hs (high- speed main) mode note 7 f mx = 10 mhz note 3 , v dd = 3.0 v resonator connection 0.26 0.67 ma square wave input 95 330 ? a f mx = 8 mhz note 3 , v dd = 3.0 v resonator connection 145 380 ? a square wave input 95 330 ? a ls (low- speed main) mode note 7 f mx = 8 mhz note 3 , v dd = 2.0 v resonator connection 145 380 ? a square wave input 0.25 0.57 ? a f sub = 32.768 khz note 5 t a = ?40 ? c resonator connection 0.44 0.76 ? a square wave input 0.30 0.57 ? a f sub = 32.768 khz note 5 t a = +25 ? c resonator connection 0.49 0.76 ? a square wave input 0.37 1.17 ? a f sub = 32.768 khz note 5 t a = +50 ? c resonator connection 0.56 1.36 ? a square wave input 0.53 1.97 ? a f sub = 32.768 khz note 5 t a = +70 ? c resonator connection 0.72 2.16 ? a square wave input 0.82 3.37 ? a i dd2 note 2 halt mode subsystem clock operation f sub = 32.768 khz note 5 t a = +85 ? c resonator connection 1.01 3.56 ? a t a = ?40 ? c 0.18 0.50 ? a t a = +25 ? c 0.23 0.50 ? a t a = +50 ? c 0.30 1.10 ? a t a = +70 ? c 0.46 1.90 ? a supply current note 1 i dd3 note 6 stop mode note 8 t a = +85 ? c 0.75 3.30 ? a (notes and remarks are listed on the next page.)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 66 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 notes 1. total current flowing into v dd and ev dd0 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 or v ss , ev ss0 . the values below the max. column include the peripheral operation current. however, not incl uding the current flowing into the a/d converter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the cu rrent flowing during data flash rewrite. 2. during halt instruction execution by flash memory. 3. when high-speed on-chip oscillator and subsystem clock are stopped. 4. when high-speed system clock and subsystem clock are stopped. 5. when high-speed on-chip oscillator and high-spee d system clock are stopped. when rtclpc = 1 and setting ultra-low current consumption (amphs1 = 1). the current flowing into the rtc is included. however, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. not including the current flowing into the rt c, 12-bit interval timer, and watchdog timer. 7. relationship between operation voltage width, operat ion frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v ? v dd ? 5.5 v@1 mhz to 32 mhz 2.4 v ? v dd ? 5.5 v@1 mhz to 16 mhz ls (low-speed main) mode: 1.8 v ? v dd ? 5.5 v@1 mhz to 8 mhz lv (low-voltage main) mode: 1.6 v ? v dd ? 5.5 v@1 mhz to 4 mhz 8. regarding the value for current to operate the subsyst em clock in stop mode, refer to that in halt mode. remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation and stop mode, temperature condition of the typ. value is t a = 25?c
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 67 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (2) flash rom: 96 to 256 kb of 30- to 100-pin products (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (1/2) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 2.3 ma basic operation v dd = 3.0 v 2.3 ma v dd = 5.0 v 5.2 8.5 ma f ih = 32 mhz note 3 normal operation v dd = 3.0 v 5.2 8.5 ma v dd = 5.0 v 4.1 6.6 ma ? f ih = 24 mhz note 3 normal operation v dd = 3.0 v 4.1 6.6 ma v dd = 5.0 v 3.0 4.7 ma ? hs (high- speed main) mode note 5 f ih = 16 mhz note 3 normal operation v dd = 3.0 v 3.0 4.7 ma v dd = 3.0 v 1.3 2.1 ma ? ls (low- speed main) mode note 5 f ih = 8 mhz note 3 normal operation v dd = 2.0 v 1.3 2.1 ma v dd = 3.0 v 1.3 1.8 ma lv ( low- voltage main) mode note 5 f ih = 4 mhz note 3 normal operation v dd = 2.0 v 1.3 1.8 ma square wave input 3.4 5.5 ma f mx = 20 mhz note 2 , v dd = 5.0 v normal operation resonator connection 3.6 5.7 ma square wave input 3.4 5.5 ma ? f mx = 20 mhz note 2 , v dd = 3.0 v normal operation resonator connection 3.6 5.7 ma square wave input 2.1 3.2 ma ? f mx = 10 mhz note 2 , v dd = 5.0 v normal operation resonator connection 2.1 3.2 ma square wave input 2.1 3.2 ma ? hs (high- speed main) mode note 5 f mx = 10 mhz note 2 , v dd = 3.0 v normal operation resonator connection 2.1 3.2 ma square wave input 1.2 2.0 ma ? f mx = 8 mhz note 2 , v dd = 3.0 v normal operation resonator connection 1.2 2.0 ma square wave input 1.2 2.0 ma ? ls (low- speed main) mode note 5 f mx = 8 mhz note 2 , v dd = 2.0 v normal operation resonator connection 1.2 2.0 ma square wave input 4.8 5.9 ? a f sub = 32.768 khz note 4 t a = ?40 ? c normal operation resonator connection 4.9 6.0 ? a square wave input 4.9 5.9 ? a f sub = 32.768 khz note 4 t a = +25 ? c normal operation resonator connection 5.0 6.0 ? a square wave input 5.0 7.6 ? a f sub = 32.768 khz note 4 t a = +50 ? c normal operation resonator connection 5.1 7.7 ? a square wave input 5.2 9.3 ? a f sub = 32.768 khz note 4 t a = +70 ? c normal operation resonator connection 5.3 9.4 ? a square wave input 5.7 13.3 ? a supply current note 1 i dd1 operating mode subsystem clock operation f sub = 32.768 khz note 4 t a = +85 ? c normal operation resonator connection 5.8 13.4 ? a (notes and remarks are listed on the next page.)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 68 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 notes 1. total current flowing into v dd , ev dd0 , and ev dd1 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 , and ev dd1 , or v ss , ev ss0 , and ev ss1 . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d converter, lvd circuit, i/o port, and on-chip pull- up/pull-down resistors and the current flowing during data flash rewrite. 2. when high-speed on-chip oscillator and subsystem clock are stopped. 3. when high-speed system clock and subsystem clock are stopped. 4. when high-speed on-chip oscillator and high-spee d system clock are stopped. when amphs1 = 1 (ultra-low power consumption oscillation). however, not including the current flowing into the 12-bit interval timer and watchdog timer. 5. relationship between operation voltage width, operat ion frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v ? v dd ? 5.5 v@1 mhz to 32 mhz 2.4 v ? v dd ? 5.5 v@1 mhz to 16 mhz ls (low-speed main) mode: 1.8 v ? v dd ? 5.5 v@1 mhz to 8 mhz lv (low-voltage main) mode: 1.6 v ? v dd ? 5.5 v@1 mhz to 4 mhz remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation, temper ature condition of t he typ. value is t a = 25 ?c
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 69 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (2) flash rom: 96 to 256 kb of 30- to 100-pin products (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/2) (notes and remarks are listed on the next page.) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 0.62 1.86 ma f ih = 32 mhz note 4 v dd = 3.0 v 0.62 1.86 ma v dd = 5.0 v 0.50 1.45 ma f ih = 24 mhz note 4 v dd = 3.0 v 0.50 1.45 ma v dd = 5.0 v 0.44 1.11 ma hs (high- speed main) mode note 7 f ih = 16 mhz note 4 v dd = 3.0 v 0.44 1.11 ma v dd = 3.0 v 290 620 ? a ls (low- speed main) mode note 7 f ih = 8 mhz note 4 v dd = 2.0 v 290 620 ? a v dd = 3.0 v 440 680 ? a lv ( low- voltage main) mode note 7 f ih = 4 mhz note 4 v dd = 2.0 v 440 680 ? a square wave input 0.31 1.08 ma f mx = 20 mhz note 3 , v dd = 5.0 v resonator connection 0.48 1.28 ma square wave input 0.31 1.08 ma f mx = 20 mhz note 3 , v dd = 3.0 v resonator connection 0.48 1.28 ma square wave input 0.21 0.63 ma f mx = 10 mhz note 3 , v dd = 5.0 v resonator connection 0.28 0.71 ma square wave input 0.21 0.63 ma hs (high- speed main) mode note 7 f mx = 10 mhz note 3 , v dd = 3.0 v resonator connection 0.28 0.71 ma square wave input 110 360 ? a f mx = 8 mhz note 3 , v dd = 3.0 v resonator connection 160 420 ? a square wave input 110 360 ? a ls (low- speed main) mode note 7 f mx = 8 mhz note 3 , v dd = 2.0 v resonator connection 160 420 ? a square wave input 0.28 0.61 ? a f sub = 32.768 khz note 5 t a = ?40 ? c resonator connection 0.47 0.80 ? a square wave input 0.34 0.61 ? a f sub = 32.768 khz note 5 t a = +25 ? c resonator connection 0.53 0.80 ? a square wave input 0.41 2.30 ? a f sub = 32.768 khz note 5 t a = +50 ? c resonator connection 0.60 2.49 ? a square wave input 0.64 4.03 ? a f sub = 32.768 khz note 5 t a = +70 ? c resonator connection 0.83 4.22 ? a square wave input 1.09 8.04 ? a i dd2 note 2 halt mode subsystem clock operation f sub = 32.768 khz note 5 t a = +85 ? c resonator connection 1.28 8.23 ? a t a = ?40 ? c 0.19 0.52 ? a t a = +25 ? c 0.25 0.52 ? a t a = +50 ? c 0.32 2.21 ? a t a = +70 ? c 0.55 3.94 ? a supply current note 1 i dd3 note 6 stop mode note 8 t a = +85 ? c 1.00 7.95 ? a
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 70 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 notes 1. total current flowing into v dd , ev dd0 , and ev dd1 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 , and ev dd1 , or v ss , ev ss0 , and ev ss1 . the values below the max. column include the peripheral operation current . however, not including the current flowing into the a/d converter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. during halt instruction execution by flash memory. 3. when high-speed on-chip oscillator and subsystem clock are stopped. 4. when high-speed system clock and subsystem clock are stopped. 5. when high-speed on-chip oscillator and high-speed system clock are stopped. when rtclpc = 1 and setting ultra-low current consumption (amphs1 = 1). the current flowing into the rtc is included. however, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. not including the current flowing into the rt c, 12-bit interval timer, and watchdog timer. 7. relationship between operation voltage width, operat ion frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v ? v dd ? 5.5 v@1 mhz to 32 mhz 2.4 v ? v dd ? 5.5 v@1 mhz to 16 mhz ls (low-speed main) mode: 1.8 v ? v dd ? 5.5 v@1 mhz to 8 mhz lv (low-voltage main) mode: 1.6 v ? v dd ? 5.5 v@1 mhz to 4 mhz 8. regarding the value for current to operate the subsyst em clock in stop mode, refer to that in halt mode. remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation and stop mode, temperature condition of the typ. value is t a = 25?c
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 71 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (3) 128-pin products, and flash rom: 384 to 512 kb of 44- to 100-pin products (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (1/2) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 2.6 ma basic operation v dd = 3.0 v 2.6 ma v dd = 5.0 v 6.1 9.5 ma f ih = 32 mhz note 3 normal operation v dd = 3.0 v 6.1 9.5 ma v dd = 5.0 v 4.8 7.4 ma ? f ih = 24 mhz note 3 normal operation v dd = 3.0 v 4.8 7.4 ma v dd = 5.0 v 3.5 5.3 ma ? hs (high- speed main) mode note 5 f ih = 16 mhz note 3 normal operation v dd = 3.0 v 3.5 5.3 ma v dd = 3.0 v 1.5 2.3 ma ? ls (low- speed main) mode note 5 f ih = 8 mhz note 3 normal operation v dd = 2.0 v 1.5 2.3 ma v dd = 3.0 v 1.5 2.0 ma ? lv ( low- voltage main) mode note 5 f ih = 4 mhz note 3 normal operation v dd = 2.0 v 1.5 2.0 ma square wave input 3.9 6.1 ma f mx = 20 mhz note 2 , v dd = 5.0 v normal operation resonator connection 4.1 6.3 ma square wave input 3.9 6.1 ma ? f mx = 20 mhz note 2 , v dd = 3.0 v normal operation resonator connection 4.1 6.3 ma square wave input 2.5 3.7 ma ? f mx = 10 mhz note 2 , v dd = 5.0 v normal operation resonator connection 2.5 3.7 ma square wave input 2.5 3.7 ma ? hs (high- speed main) mode note 5 f mx = 10 mhz note 2 , v dd = 3.0 v normal operation resonator connection 2.5 3.7 ma square wave input 1.4 2.2 ma ? f mx = 8 mhz note 2 , v dd = 3.0 v normal operation resonator connection 1.4 2.2 ma square wave input 1.4 2.2 ma ? ls (low- speed main) mode note 5 f mx = 8 mhz note 2 , v dd = 2.0 v normal operation resonator connection 1.4 2.2 ma square wave input 5.4 6.5 ? a f sub = 32.768 khz note 4 t a = ?40 ? c normal operation resonator connection 5.5 6.6 ? a square wave input 5.5 6.5 ? a f sub = 32.768 khz note 4 t a = +25 ? c normal operation resonator connection 5.6 6.6 ? a square wave input 5.6 9.4 ? a f sub = 32.768 khz note 4 t a = +50 ? c normal operation resonator connection 5.7 9.5 ? a square wave input 5.9 12.0 ? a f sub = 32.768 khz note 4 t a = +70 ? c normal operation resonator connection 6.0 12.1 ? a square wave input 6.6 16.3 ? a supply current note 1 i dd1 operating mode subsystem clock operation f sub = 32.768 khz note 4 t a = +85 ? c normal operation resonator connection 6.7 16.4 ? a (notes and remarks are listed on the next page.)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 72 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 notes 1. total current flowing into v dd , ev dd0 , and ev dd1 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 , and ev dd1 , or v ss , ev ss0 , and ev ss1 . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d converter, lvd circuit, i/o port, and on-chip pull- up/pull-down resistors and the current flowing during data flash rewrite. 2. when high-speed on-chip oscillator and subsystem clock are stopped. 3. when high-speed system clock and subsystem clock are stopped. 4. when high-speed on-chip oscillator and high-spee d system clock are stopped. when amphs1 = 1 (ultra-low power consumption oscillation). however, not including the current fl owing into the rtc, 12-bit interval timer, and watchdog timer. 5. relationship between operation voltage width, operat ion frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v ? v dd ? 5.5 v@1 mhz to 32 mhz 2.4 v ? v dd ? 5.5 v@1 mhz to 16 mhz ls (low-speed main) mode: 1.8 v ? v dd ? 5.5 v @1 mhz to 8 mhz lv (low-voltage main) mode: 1.6 v ? v dd ? 5.5 v@1 mhz to 4 mhz remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation, temper ature condition of t he typ. value is t a = 25 ?c
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 73 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (3) 128-pin products, and flash rom: 384 to 512 kb of 44- to 100-pin products (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/2) (notes and remarks are listed on the next page.) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 0.62 1.89 ma f ih = 32 mhz note 4 v dd = 3.0 v 0.62 1.89 ma v dd = 5.0 v 0.50 1.48 ma f ih = 24 mhz note 4 v dd = 3.0 v 0.50 1.48 ma v dd = 5.0 v 0.44 1.12 ma hs (high- speed main) mode note 7 f ih = 16 mhz note 4 v dd = 3.0 v 0.44 1.12 ma v dd = 3.0 v 290 620 ? a ls (low- speed main) mode note 7 f ih = 8 mhz note 4 v dd = 2.0 v 290 620 ? a v dd = 3.0 v 460 700 ? a lv ( low- voltage main) mode note 7 f ih = 4 mhz note 4 v dd = 2.0 v 460 700 ? a square wave input 0.31 1.14 ma f mx = 20 mhz note 3 , v dd = 5.0 v resonator connection 0.48 1.34 ma square wave input 0.31 1.14 ma f mx = 20 mhz note 3 , v dd = 3.0 v resonator connection 0.48 1.34 ma square wave input 0.21 0.68 ma f mx = 10 mhz note 3 , v dd = 5.0 v resonator connection 0.28 0.76 ma square wave input 0.21 0.68 ma hs (high- speed main) mode note 7 f mx = 10 mhz note 3 , v dd = 3.0 v resonator connection 0.28 0.76 ma square wave input 110 390 ? a f mx = 8 mhz note 3 , v dd = 3.0 v resonator connection 160 450 ? a square wave input 110 390 ? a ls (low- speed main) mode note 7 f mx = 8 mhz note 3 , v dd = 2.0 v resonator connection 160 450 ? a square wave input 0.31 0.66 ? a f sub = 32.768 khz note 5 t a = ?40 ? c resonator connection 0.50 0.85 ? a square wave input 0.38 0.66 ? a f sub = 32.768 khz note 5 t a = +25 ? c resonator connection 0.57 0.85 ? a square wave input 0.47 3.49 ? a f sub = 32.768 khz note 5 t a = +50 ? c resonator connection 0.66 3.68 ? a square wave input 0.80 6.10 ? a f sub = 32.768 khz note 5 t a = +70 ? c resonator connection 0.99 6.29 ? a square wave input 1.52 10.46 ? a i dd2 note 2 halt mode subsystem clock operation f sub = 32.768 khz note 5 t a = +85 ? c resonator connection 1.71 10.65 ? a t a = ?40 ? c 0.19 0.54 ? a t a = +25 ? c 0.26 0.54 ? a t a = +50 ? c 0.35 3.37 ? a t a = +70 ? c 0.68 5.98 ? a supply current note 1 i dd3 note 6 stop mode note 8 t a = +85 ? c 1.40 10.34 ? a
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 74 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 notes 1. total current flowing into v dd , ev dd0 , and ev dd1 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 , and ev dd1 , or v ss , ev ss0 , and ev ss1 . the values below the max. column include the peripheral operation current . however, not including the current flowing into the a/d converter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. during halt instruction execution by flash memory. 3. when high-speed on-chip oscillator and subsystem clock are stopped. 4. when high-speed system clock and subsystem clock are stopped. 5. when high-speed on-chip oscillator and high-spee d system clock are stopped. when rtclpc = 1 and setting ultra-low current consumption (amphs1 = 1). the current flowing into the rtc is included. however, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. not including the current flowing into the rt c, 12-bit interval timer, and watchdog timer. 7. relationship between operation voltage width, operat ion frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v ? v dd ? 5.5 v@1 mhz to 32 mhz 2.4 v ? v dd ? 5.5 v@1 mhz to 16 mhz ls (low-speed main) mode: 1.8 v ? v dd ? 5.5 v @1 mhz to 8 mhz lv (low-voltage main) mode: 1.6 v ? v dd ? 5.5 v@1 mhz to 4 mhz 8. regarding the value for current to operate the subsyst em clock in stop mode, refer to that in halt mode. remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation and stop mode, temperature condition of the typ. value is t a = 25?c
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 75 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (4) peripheral functions (common to all products) (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit low-speed on- chip oscillator operating current i fil note 1 0.20 ? a rtc operating current i rtc notes 1, 2, 3 0.02 ? a 12-bit interval timer operating current i it notes 1, 2, 4 0.02 ? a watchdog timer operating current i wdt notes 1, 2, 5 f il = 15 khz 0.22 ? a normal mode, av refp = v dd = 5.0 v 1.3 1.7 ma a/d converter operating current i adc notes 1, 6 when conversion at maximum speed low voltage mode, av refp = v dd = 3.0 v 0.5 0.7 ma a/d converter reference voltage current i adref note 1 75.0 ? a temperature sensor operating current i tmps note 1 75.0 ? a lvd operating current i lvi notes 1, 7 0.08 ? a self- programming operating current i fsp notes 1, 9 2.50 12.20 ma bgo operating current i bgo notes 1, 8 2.50 12.20 ma the mode is performed note 10 0.50 0.60 ma adc operation the a/d conversion operations are performed, low voltage mode, av refp = v dd = 3.0 v 1.20 1.44 ma snooze operating current i snoz note 1 csi/uart operation 0.70 0.84 ma notes 1. current flowing to v dd . 2. when high speed on-chip oscillator and high-speed system clock are stopped. 3. current flowing only to the real-time clock (rtc) (e xcluding the operating current of the low-speed on- chip oscillator and the xt1 oscillator). the supply curr ent of the rl78 microcontro llers is the sum of the values of either i dd1 or i dd2 , and i rtc , when the real-time clock operates in operation mode or halt mode. when the low-speed on-chip o scillator is selected, i fil should be added. i dd2 subsystem clock operation includes the operational current of the real-time clock. 4. current flowing only to the 12-bit interval timer (e xcluding the operating current of the low-speed on-chip oscillator and the xt1 oscillator). the supply current of the rl78 mi crocontrollers is the sum of the values of either i dd1 or i dd2 , and i it , when the 12-bit interval timer operates in operation mode or halt mode. when the low-speed on-chi p oscillator is selected, i fil should be added. 5. current flowing only to the watchdog timer (inclu ding the operating current of the low-speed on-chip oscillator). the supply current of t he rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i wdt when the watchdog timer is in operation.
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 76 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 6. current flowing only to the a/d converter. the supply current of the rl78 microcontrollers is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. 7. current flowing only to the lvd circuit. the supply cu rrent of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i lvd when the lvd circuit is in operation. 8. current flowing only during data flash rewrite. 9. current flowing only during self programming. 10. for shift time to the snooze mode, see 18.3.3 snooze mode. remarks 1. f il : low-speed on-chip oscillator clock frequency 2. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 3. f clk : cpu/peripheral hardware clock frequency 4. temperature condition of the typ. value is t a = 25 ?c
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 77 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 2.4 ac characteristics (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) items symbol conditions min. typ. max. unit 2.7 v ? v dd ? 5.5 v 0.03125 1 ? s hs (high- speed main) mode 2.4 v ? v dd < 2.7 v 0.0625 1 ? s ls (low-speed main) mode 1.8 v ? v dd ? 5.5 v 0.125 1 ? s main system clock (f main ) operation lv (low- voltage main) mode 1.6 v ? v dd ? 5.5 v 0.25 1 ? s subsystem clock (f sub ) operation 1.8 v ? v dd ? 5.5 v 28.5 30.5 31.3 ? s 2.7 v ? v dd ? 5.5 v 0.03125 1 ? s hs (high- speed main) mode 2.4 v ? v dd < 2.7 v 0.0625 1 ? s ls (low-speed main) mode 1.8 v ? v dd ? 5.5 v 0.125 1 ? s instruction cycle (minimum instruction execution time) t cy in the self programming mode lv (low- voltage main) mode 1.8 v ? v dd ? 5.5 v 0.25 1 ? s 2.7 v ? v dd ? 5.5 v 1.0 20.0 mhz 2.4 v ? v dd < 2.7 v 1.0 16.0 mhz 1.8 v ? v dd < 2.4 v 1.0 8.0 mhz f ex 1.6 v ? v dd < 1.8 v 1.0 4.0 mhz external system clock frequency f exs 32 35 khz 2.7 v ? v dd ? 5.5 v 24 ns 2.4 v ? v dd < 2.7 v 30 ns 1.8 v ? v dd < 2.4 v 60 ns t exh , t exl 1.6 v ? v dd < 1.8 v 120 ns external system clock input high-level width, low-level width t exhs , t exls 13.7 ? s ti00 to ti07, ti10 to ti17 input high-level width, low-level width t tih , t til 1/f mck +10 ns note 4.0 v ? ev dd0 ? 5.5 v 16 mhz 2.7 v ? ev dd0 < 4.0 v 8 mhz 1.8 v ? ev dd0 < 2.7 v 4 mhz hs (high-speed main) mode 1.6 v ? ev dd0 < 1.8 v 2 mhz 1.8 v ? ev dd0 ? 5.5 v 4 mhz ls (low-speed main) mode 1.6 v ? ev dd0 < 1.8 v 2 mhz to00 to to07, to10 to to17 output frequency f to lv (low-voltage main) mode 1.6 v ? ev dd0 ? 5.5 v 2 mhz 4.0 v ? ev dd0 ? 5.5 v 16 mhz 2.7 v ? ev dd0 < 4.0 v 8 mhz 1.8 v ? ev dd0 < 2.7 v 4 mhz hs (high-speed main) mode 1.6 v ? ev dd0 < 1.8 v 2 mhz 1.8 v ? ev dd0 ? 5.5 v 4 mhz ls (low-speed main) mode 1.6 v ? ev dd0 < 1.8 v 2 mhz 1.8 v ? ev dd0 ? 5.5 v 4 mhz pclbuz0, pclbuz1 output frequency f pcl lv (low-voltage main) mode 1.6 v ? ev dd0 < 1.8 v 2 mhz intp0 1.6 v ? v dd ? 5.5 v 1 ? s interrupt input high-level width, low-level width t inth , t intl intp1 to intp11 1.6 v ? ev dd0 ? 5.5 v 1 ? s 1.8 v ? ev dd0 ? 5.5 v 250 ns key interrupt input low-level width t kr kr0 to kr7 1.6 v ? ev dd0 < 1.8 v 1 ? s reset low-level width t rsl 10 ? s (note and remark are listed on the next page.)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 78 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 note the following conditions are required for low voltage interface when e vdd0 < v dd 1.8 v ? ev dd0 < 2.7 v : min. 125 ns 1.6 v ? ev dd0 < 1.8 v : min. 250 ns remark f mck : timer array unit operation clock frequency (operation clock to be set by the cksmn0, cksmn1 bits of timer mode register mn (tmrmn). m: unit number (m = 0, 1), n: channel number (n = 0 to 7)) minimum instruction execution time dur ing main system clock operation t cy vs v dd (hs (high-speed main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 0.01 2.4 0.03125 0.0625 0.05 when the high-speed on-chip oscillator clock is selected during self programming when high-speed system clock is selected cycle time t cy [s] supply voltage v dd [v]
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 79 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 t cy vs v dd (ls (low-speed main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 0.01 1.8 0.125 cycle time t cy [s] supply voltage v dd [v] when the high-speed on-chip oscillator clock is selected during self programming when high-speed system clock is selected t cy vs v dd (lv (low-voltage main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 0.01 1.8 0.25 1.6 cycle time t cy [s] supply voltage v dd [v] when the high-speed on-chip oscillator clock is selected during self programming when high-speed system clock is selected
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 80 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 ac timing test points v ih /v oh v il /v ol test points v ih /v oh v il /v ol external system clock timing exclk/exclks 1/f ex / 1/f exs t exl / t exls t exh / t exhs ti/to timing ti00 to ti07, ti10 to ti17 t til t tih to00 to to07, to10 to to17 1/f to interrupt request input timing intp0 to intp11 t intl t inth key interrupt input timing kr0 to kr7 t kr reset input timing reset t rsl
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 81 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 2.5 peripheral functions characteristics ac timing test points v ih /v oh v il /v ol test points v ih /v oh v il /v ol 2.5.1 serial array unit (1) during communication at same potential (uart mode) (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit 2.4 v ? ev dd0 ? 5.5 v f mck /6 note 2 f mck /6 f mck /6 bps theoretical value of the maximum transfer rate f mck = f clk note 3 5.3 1.3 0.6 mbps 1.8 v ? ev dd0 ? 5.5 v f mck /6 note 2 f mck /6 f mck /6 bps theoretical value of the maximum transfer rate f mck = f clk note 3 5.3 1.3 0.6 mbps 1.7 v ? ev dd0 ? 5.5 v f mck /6 note 2 f mck /6 note 2 f mck /6 bps theoretical value of the maximum transfer rate f mck = f clk note 3 5.3 1.3 0.6 mbps 1.6 v ? ev dd0 ? 5.5 v ? f mck /6 note 2 f mck /6 bps transfer rate note 1 theoretical value of the maximum transfer rate f mck = f clk note 3 ? 1.3 0.6 mbps notes 1. transfer rate in the snooze mode is 4800 bps only. 2. the following conditions are required for low voltage interface when e vdd0 < v dd . 2.4 v ? ev dd0 < 2.7 v : max. 2.6 mbps 1.8 v ? ev dd0 < 2.4 v : max. 1.3 mbps 1.6 v ? ev dd0 < 1.8 v : max. 0.6 mbps 3. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main) mode: 32 mhz (2.7 v ? v dd ? 5.5 v) 16 mhz (2.4 v ? v dd ? 5.5 v) ls (low-speed main) mode: 8 mhz (1.8 v ? v dd ? 5.5 v) lv (low-voltage main ) mode: 4 mhz (1.6 v ? v dd ? 5.5 v) caution select the normal input buffer for the rxdq pi n and the normal output mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg).
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 82 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 uart mode connection diagram (duri ng communication at same potential) rl78 microcontroller txdq rxdq rx tx user device uart mode bit width (dur ing communication at same potential) (reference) baud rate error tolerance high-/low-bit width 1/transfer rate txdq rxdq remarks 1. q: uart number (q = 0 to 3), g: pim and pom number (g = 0, 1, 8, 14) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13))
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 83 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (2) during communication at same pot ential (csi mode) (master mode , sckp... internal clock output, corresponding csi00 only) (t a = ? 40 to +85 ? c, 2.7 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit 4.0 v ? ev dd0 ? 5.5 v 62.5 250 500 ns sckp cycle time t kcy1 t kcy1 ? 2/f clk 2.7 v ? ev dd0 ? 5.5 v 83.3 250 500 ns 4.0 v ? ev dd0 ? 5.5 v t kcy1 /2 ? 7 t kcy1 /2 ? 50 t kcy1 /2 ? 50 ns sckp high-/low-level width t kh1 , t kl1 2.7 v ? ev dd0 ? 5.5 v t kcy1 /2 ? 10 t kcy1 /2 ? 50 t kcy1 /2 ? 50 ns 4.0 v ? ev dd0 ? 5.5 v 23 110 110 ns sip setup time (to sckp ? ) note 1 t sik1 2.7 v ? ev dd0 ? 5.5 v 33 110 110 ns sip hold time (from sckp ? ) note 2 t ksi1 2.7 v ? ev dd0 ? 5.5 v 10 10 10 ns delay time from sckp ? to sop output note 3 t kso1 c = 20 pf note 4 10 10 10 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port ou tput mode register g (pomg). remarks 1. this value is valid only when csi00?s peripheral i/o redirect function is not used. 2. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom numbers (g = 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00))
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 84 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (3) during communication at same potential (csi mode) (master mode, sckp... internal clock output) (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port ou tput mode register g (pomg). hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit 2.7 v ? ev dd0 ? 5.5 v 125 500 1000 ns 2.4 v ? ev dd0 ? 5.5 v 250 500 1000 ns 1.8 v ? ev dd0 ? 5.5 v 500 500 1000 ns 1.7 v ? ev dd0 ? 5.5 v 1000 1000 1000 ns sckp cycle time t kcy1 t kcy1 ? 4/f clk 1.6 v ? ev dd0 ? 5.5 v ? 1000 1000 ns 4.0 v ? ev dd0 ? 5.5 v t kcy1 /2 ? 12 t kcy1 /2 ? 50 t kcy1 /2 ? 50 ns 2.7 v ? ev dd0 ? 5.5 v t kcy1 /2 ? 18 t kcy1 /2 ? 50 t kcy1 /2 ? 50 ns 2.4 v ? ev dd0 ? 5.5 v t kcy1 /2 ? 38 t kcy1 /2 ? 50 t kcy1 /2 ? 50 ns 1.8 v ? ev dd0 ? 5.5 v t kcy1 /2 ? 50 t kcy1 /2 ? 50 t kcy1 /2 ? 50 ns 1.7 v ? ev dd0 ? 5.5 v t kcy1 /2 ? 100 t kcy1 /2 ? 100 t kcy1 /2 ? 100 ns sckp high-/low-level width t kh1 , t kl1 1.6 v ? ev dd0 ? 5.5 v ? t kcy1 /2 ? 100 t kcy1 /2 ? 100 ns 4.0 v ? ev dd0 ? 5.5 v 44 110 110 ns 2.7 v ? ev dd0 ? 5.5 v 44 110 110 ns 2.4 v ? ev dd0 ? 5.5 v 75 110 110 ns 1.8 v ? ev dd0 ? 5.5 v 110 110 110 ns 1.7 v ? ev dd0 ? 5.5 v 220 220 220 ns sip setup time (to sckp ? ) note 1 t sik1 1.6 v ? ev dd0 ? 5.5 v ? 220 220 ns 1.7 v ? ev dd0 ? 5.5 v 19 19 19 ns sip hold time (from sckp ? ) note 2 t ksi1 1.6 v ? ev dd0 ? 5.5 v ? 19 19 ns 1.7 v ? ev dd0 ? 5.5 v c = 30 pf note 4 25 25 25 ns delay time from sckp ? to sop output note 3 t kso1 1.6 v ? ev dd0 ? 5.5 v c = 30 pf note 4 ? 25 25 ns
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 85 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 remarks 1. p: csi number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom numbers (g = 0, 1, 4, 5, 8, 14) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) (4) during communication at same potential (csi mode) (slave mode, sckp... external clock input) (1/2) (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit 20 mhz < f mck 8/f mck ? ? ns 4.0 v ? ev dd0 ? 5.5 v f mck ? 20 mhz 6/f mck 6/f mck 6/f mck ns 16 mhz < f mck 8/f mck ? ? ns 2.7 v ? ev dd0 ? 5.5 v f mck ? 16 mhz 6/f mck 6/f mck 6/f mck ns 2.4 v ? ev dd0 ? 5.5 v 6/f mck and 500 6/f mck and 500 6/f mck and 500 ns 1.8 v ? ev dd0 ? 5.5 v 6/f mck and 750 6/f mck and 750 6/f mck and 750 ns 1.7 v ? ev dd0 ? 5.5 v 6/f mck and 1500 6/f mck and 1500 6/f mck and 1500 ns sckp cycle time note 5 t kcy2 1.6 v ? ev dd0 ? 5.5 v ? 6/f mck and 1500 6/f mck and 1500 ns 4.0 v ? ev dd0 ? 5.5 v t kcy2 /2 ? 7 t kcy2 /2 ? 7 t kcy2 /2 ? 7 ns 2.7 v ? ev dd0 ? 5.5 v t kcy2 /2 ? 8 t kcy2 /2 ? 8 t kcy2 /2 ? 8 ns 1.8 v ? ev dd0 ? 5.5 v t kcy2 /2 ? 18 t kcy2 /2 ? 18 t kcy2 /2 ? 18 ns 1.7 v ? ev dd0 ? 5.5 v t kcy2 /2 ? 66 t kcy2 /2 ? 66 t kcy2 /2 ? 66 ns sckp high-/low- level width t kh2 , t kl2 1.6 v ? ev dd0 ? 5.5 v ? t kcy2 /2 ? 66 t kcy2 /2 ? 66 ns (notes , caution , and remarks are listed on the next page.)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 86 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (4) during communication at same potential (csi mode) (slave mode, sckp... external clock input) (2/2) (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode parameter symbo l conditions min. max. min. max. min. max. unit 2.7 v ? ev dd0 ? 5.5 v 1/f mck +2 0 1/f mck +30 1/f mck +30 ns 1.8 v ? ev dd0 ? 5.5 v 1/f mck +3 0 1/f mck +30 1/f mck +30 ns 1.7 v ? ev dd0 ? 5.5 v 1/f mck +4 0 1/f mck +40 1/f mck +40 ns sip setup time (to sckp ? ) note 1 t sik2 1.6 v ? ev dd0 ? 5.5 v ? 1/f mck +40 1/f mck +40 ns 1.8 v ? ev dd0 ? 5.5 v 1/f mck +3 1 1/f mck +31 1/f mck +31 ns 1.7 v ? ev dd0 ? 5.5 v 1/f mck + 250 1/f mck + 250 1/f mck + 250 ns sip hold time (from sckp ? ) note 2 t ksi2 1.6 v ? ev dd0 ? 5.5 v ? 1/f mck + 250 1/f mck + 250 ns 2.7 v ? ev dd0 ? 5.5 v 2/f mck + 44 2/f mck + 110 2/f mck + 110 ns 2.4 v ? ev dd0 ? 5.5 v 2/f mck + 75 2/f mck + 110 2/f mck + 110 ns 1.8 v ? ev dd0 ? 5.5 v 2/f mck + 110 2/f mck + 110 2/f mck + 110 ns 1.7 v ? ev dd0 ? 5.5 v 2/f mck + 220 2/f mck + 220 2/f mck + 220 ns delay time from sckp ? to sop output note 3 t kso2 c = 30 pf note 4 1.6 v ? ev dd0 ? 5.5 v ? 2/f mck + 220 2/f mck + 220 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sop output lines. 5. transfer rate in the snooze mode: max. 1 mbps caution select the normal input buffer for the sip pi n and sckp pin and the normal output mode for the sop pin by using port input mode register g (pimg) and port out put mode register g (pomg). remarks 1. p: csi number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pi m number (g = 0, 1, 4, 5, 8, 14) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13))
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 87 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 csi mode connection diagram (during communication at same potential) rl78 microcontroller sckp sop sck si user device sip so csi mode serial transfer timing (during communication at same potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy1, 2 t kl1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp csi mode serial transfer timing (during communication at same potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy1, 2 t kh1, 2 t kl1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp remarks 1. p: csi number (p = 00, 01, 10, 11, 20, 21, 30, 31) 2. m: unit number, n: channel number (mn = 00 to 03, 10 to 13)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 88 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (5) during communication at sam e potential (simplified i 2 c mode) (1/2) (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit 2.7 v ? ev dd0 ? 5.5 v, c b = 50 pf, r b = 2.7 k ? 1000 note 1 400 note 1 400 note 1 khz 1.8 v ? ev dd0 ? 5.5 v, c b = 100 pf, r b = 3 k ? 400 note 1 400 note 1 400 note 1 khz 1.8 v ? ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k ? 300 note 1 300 note 1 300 note 1 khz 1.7 v ? ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? 250 note 1 250 note 1 250 note 1 khz sclr clock frequency f scl 1.6 v ? ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? ? 250 note 1 250 note 1 khz 2.7 v ? ev dd0 ? 5.5 v, c b = 50 pf, r b = 2.7 k ? 475 1150 1150 ns 1.8 v ? ev dd0 ? 5.5 v, c b = 100 pf, r b = 3 k ? 1150 1150 1150 ns 1.8 v ? ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k ? 1550 1550 1550 ns 1.7 v ? ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? 1850 1850 1850 ns hold time when sclr = ?l? t low 1.6 v ? ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? ? 1850 1850 ns 2.7 v ? ev dd0 ? 5.5 v, c b = 50 pf, r b = 2.7 k ? 475 1150 1150 ns 1.8 v ? ev dd0 ? 5.5 v, c b = 100 pf, r b = 3 k ? 1150 1150 1150 ns 1.8 v ? ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k ? 1550 1550 1550 ns 1.7 v ? ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? 1850 1850 1850 ns hold time when sclr = ?h? t high 1.6 v ? ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? ? 1850 1850 ns (notes and caution are listed on the next page, and remarks are listed on the page after the next page.)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 89 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (5) during communication at sam e potential (simplified i 2 c mode) (2/2) (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit 2.7 v ? ev dd0 ? 5.5 v, c b = 50 pf, r b = 2.7 k ? 1/f mck + 85 note2 1/f mck + 145 note2 1/f mck + 145 note2 ns 1.8 v ? ev dd0 ? 5.5 v, c b = 100 pf, r b = 3 k ? 1/f mck + 145 note2 1/f mck + 145 note2 1/f mck + 145 note2 ns 1.8 v ? ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k ? 1/f mck + 230 note2 1/f mck + 230 note2 1/f mck + 230 note2 ns 1.7 v ? ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? 1/f mck + 290 note2 1/f mck + 290 note2 1/f mck + 290 note2 ns data setup time (reception) t su:dat 1.6 v ? ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? ? 1/f mck + 290 note2 1/f mck + 290 note2 ns 2.7 v ? ev dd0 ? 5.5 v, c b = 50 pf, r b = 2.7 k ? 0 305 0 305 0 305 ns 1.8 v ? ev dd0 ? 5.5 v, c b = 100 pf, r b = 3 k ? 0 355 0 355 0 355 ns 1.8 v ? ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k ? 0 405 0 405 0 405 ns 1.7 v ? ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? 0 405 0 405 0 405 ns data hold time (transmission) t hd:dat 1.6 v ? ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? ? 0 405 0 405 ns notes 1. the value must also be equal to or less than f mck /4. 2. set the f mck value to keep the hold time of sclr = "l" and sclr = "h". caution select the normal input buffe r and the n-ch open drain output (v dd tolerance (when 20- to 52-pin products)/ev dd tolerance (when 64- to 128-pin products )) mode for the sdar pin and the normal output mode for the sclr pin by using port input mode register g (pimg) and port output mode register h (pomh). ( remarks are listed on the next page.)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 90 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 simplified i 2 c mode mode connection diagram (dur ing communication at same potential) rl78 microcontroller sdar sclr sda scl user device v dd r b simplified i 2 c mode serial transfer timing (dur ing communication at same potential) sdar t low t high t hd:dat sclr t su:dat 1/f scl remarks 1. r b [ ? ]:communication line (sdar) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance 2. r: iic number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: pim number (g = 0, 1, 4, 5, 8, 14), h: pom number (g = 0, 1, 4, 5, 7 to 9, 14) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number (m = 0, 1), n: channel number (n = 0 to 3), mn = 00 to 03, 10 to 13)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 91 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (6) communication at different potential (1.8 v, 2.5 v, 3 v) (uart mode) (1/2) (t a = ? 40 to +85 ? c, 1.8 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high- speed main) mode ls (low-speed main) mode lv (low- voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit f mck /6 note 1 f mck /6 note 1 f mck /6 note 1 bps 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v theoretical value of the maximum transfer rate f mck = f clk note 4 5.3 1.3 0.6 mbps f mck /6 note 1 f mck /6 note 1 f mck /6 note 1 bps 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v theoretical value of the maximum transfer rate f mck = f clk note 4 5.3 1.3 0.6 mbps f mck /6 notes 1 to 3 f mck /6 notes 1, 2 f mck /6 notes 1, 2 bps transfer rate recep- tion 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v theoretical value of the maximum transfer rate f mck = f clk note 4 5.3 1.3 0.6 mbps notes 1. transfer rate in the snooze mode is 4800 bps only. 2. use it with ev dd0 ? v b . 3. the following conditions are required for low voltage interface when e vdd0 < v dd . 2.4 v ? ev dd0 < 2.7 v : max. 2.6 mbps 1.8 v ? ev dd0 < 2.4 v : max. 1.3 mbps 4. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main) mode: 32 mhz (2.7 v ? v dd ? 5.5 v) 16 mhz (2.4 v ? v dd ? 5.5 v) ls (low-speed main) mode: 8 mhz (1.8 v ? v dd ? 5.5 v) lv (low-voltage main ) mode: 4 mhz (1.6 v ? v dd ? 5.5 v) caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance (when 20- to 52-pin products)/ev dd tolerance (when 64- to 128-pin produc ts)) mode for the txdq pin by using port input mode register g (pimg) and port output m ode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remarks 1. v b [v]: communication line voltage 2. q: uart number (q = 0 to 3), g: pi m and pom number (g = 0, 1, 8, 14) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13) 4. uart2 cannot communicate at di fferent potential when bit 1 (pior 1) of peripheral i/o redirection register (pior) is 1.
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 92 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (6) communication at different potential (1.8 v, 2.5 v, 3 v) (uart mode) (2/2) (t a = ? 40 to +85 ? c, 1.8 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high- speed main) mode ls (low- speed main) mode lv (low- voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit note 1 note 1 note 1 bps 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v theoretical value of the maximum transfer rate c b = 50 pf, r b = 1.4 k ? , v b = 2.7 v 2.8 note 2 2.8 note 2 2.8 note 2 mbps note 3 note 3 note 3 bps 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v theoretical value of the maximum transfer rate c b = 50 pf, r b = 2.7 k ? , v b = 2.3 v 1.2 note 4 1.2 note 4 1.2 note 4 mbps notes 5, 6 notes 5, 6 notes 5, 6 bps transfer rate transmission 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v theoretical value of the maximum transfer rate c b = 50 pf, r b = 5.5 k ? , v b = 1.6 v 0.43 note 7 0.43 note 7 0.43 note 7 mbps notes 1. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 4.0 v ? ev dd0 ? 5.5 v and 2.7 v ? v b ? 4.0 v 1 maximum transfer rate = [bps] { ? c b r b ln (1 ? 2.2 v b )} 3 1 transfer rate ? 2 ? { ? c b r b ln (1 ? 2.2 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical va lue of the relative difference betwee n the transmission and reception sides. 2. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 1 above to calculate the maxi mum transfer rate under conditions of the customer.
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 93 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 3. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v ? ev dd0 < 4.0 v and 2.3 v ? v b ? 2.7 v 1 maximum transfer rate = { ? c b r b ln (1 ? 2.0 v b )} 3 [bps] 1 transfer rate ? 2 ? { ? c b r b ln (1 ? 2.0 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical va lue of the relative difference betwee n the transmission and reception sides. 4. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 3 above to calculate the maxi mum transfer rate under conditions of the customer. 5. use it with ev dd0 ? v b . 6. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 1.8 v ? ev dd0 < 3.3 v and 1.6 v ? v b ? 2.0 v 1 maximum transfer rate = [bps] { ? c b r b ln (1 ? 1.5 v b )} 3 1 transfer rate ? 2 ? { ? c b r b ln (1 ? 1.5 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical va lue of the relative difference betwee n the transmission and reception sides. 7. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 6 above to calculate the maxi mum transfer rate under conditions of the customer. caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance (when 20- to 52-pin products)/ev dd tolerance (when 64- to 128-pin prod ucts)) mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. uart mode connection diagram (during communication at different potential) rl78 microcontroller txdq rxdq rx tx user device v b r b
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 94 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 uart mode bit width (during communication at different potential) (reference) txdq rxdq baud rate error tolerance baud rate error tolerance low-bit width high-/low-bit width high-bit width 1/transfer rate 1/transfer rate remarks 1. r b [ ? ]:communication line (txdq) pull-up resistance, c b [f]: communication line (txdq) load capacitance, v b [v]: communication line voltage 2. q: uart number (q = 0 to 3), g: pi m and pom number (g = 0, 1, 8, 14) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) 4. uart2 cannot communicate at different potential when bit 1 (pior1) of peripheral i/o redirection register (pior) is 1.
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 95 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (7) communication at different potentia l (2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output, corresponding csi00 only) (1/2) (t a = ? 40 to +85 ? c, 2.7 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 20 pf, r b = 1.4 k ? 200 1150 1150 ns sckp cycle time t kcy1 t kcy1 ? 2/f clk 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 20 pf, r b = 2.7 k ? 300 1150 1150 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 20 pf, r b = 1.4 k ? t kcy1 /2 ? 50 t kcy1 /2 ? 50 t kcy1 /2 ? 50 ns sckp high-level width t kh1 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 20 pf, r b = 2.7 k ? t kcy1 /2 ? 120 t kcy1 /2 ? 120 t kcy1 /2 ? 120 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 20 pf, r b = 1.4 k ? t kcy1 /2 ? 7 t kcy1 /2 ? 50 t kcy1 /2 ? 50 ns sckp low-level width t kl1 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 20 pf, r b = 2.7 k ? t kcy1 /2 ? 10 t kcy1 /2 ? 50 t kcy1 /2 ? 50 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 20 pf, r b = 1.4 k ? 58 479 479 ns sip setup time (to sckp ? ) note 1 t sik1 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 20 pf, r b = 2.7 k ? 121 479 479 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 20 pf, r b = 1.4 k ? 10 10 10 ns sip hold time (from sckp ? ) note 1 t ksi1 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 20 pf, r b = 2.7 k ? 10 10 10 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 20 pf, r b = 1.4 k ? 60 60 60 ns delay time from sckp ? to sop output note 1 t kso1 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 20 pf, r b = 2.7 k ? 130 130 130 ns (notes, caution, and remarks are listed on the next page.)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 96 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (7) communication at different potentia l (2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output, corresponding csi00 only) (2/2) (t a = ? 40 to +85 ? c, 2.7 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 20 pf, r b = 1.4 k ? 23 110 110 ns sip setup time (to sckp ? ) note 2 t sik1 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 20 pf, r b = 2.7 k ? 33 110 110 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 20 pf, r b = 1.4 k ? 10 10 10 ns sip hold time (from sckp ? ) note 2 t ksi1 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 20 pf, r b = 2.7 k ? 10 10 10 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 20 pf, r b = 1.4 k ? 10 10 10 ns delay time from sckp ? to sop output note 2 t kso1 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 20 pf, r b = 2.7 k ? 10 10 10 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. 2. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (when 20- to 52-pin products)/ev dd tolerance (when 64- to 128-pin pr oducts)) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port outp ut mode register g (pomg). for v ih and v il , see the dc characteristics wit h ttl input buffer selected. remarks 1. r b [ ? ]:communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) 4. this value is valid only when csi00?s peripheral i/o redirect function is not used.
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 97 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (8) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (1/3) (t a = ? 40 to +85 ? c, 1.8 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? 300 1150 1150 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 500 1150 1150 ns sckp cycle time t kcy1 t kcy1 ? 4/f clk 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v note , c b = 30 pf, r b = 5.5 k ? 1150 1150 1150 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? t kcy1 /2 ? 75 t kcy1 /2 ? 75 t kcy1 /2 ? 75 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? t kcy1 /2 ? 170 t kcy1 /2 ? 170 t kcy1 /2 ? 170 ns sckp high-level width t kh1 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v note , c b = 30 pf, r b = 5.5 k ? t kcy1 /2 ? 458 t kcy1 /2 ? 458 t kcy1 /2 ? 458 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? t kcy1 /2 ? 12 t kcy1 /2 ? 50 t kcy1 /2 ? 50 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? t kcy1 /2 ? 18 t kcy1 /2 ? 50 t kcy1 /2 ? 50 ns sckp low-level width t kl1 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v note , c b = 30 pf, r b = 5.5 k ? t kcy1 /2 ? 50 t kcy1 /2 ? 50 t kcy1 /2 ? 50 ns note use it with ev dd0 ? v b . caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (when 20- to 52-pin products)/ev dd tolerance (when 64- to 128-pin pr oducts)) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port outp ut mode register g (pomg). for v ih and v il , see the dc characteristics wit h ttl input buffer selected. (remarks are listed two pages after the next page.)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 98 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (8) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (2/3) (t a = ? 40 to +85 ? c, 1.8 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? 81 479 479 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 177 479 479 ns sip setup time (to sckp ? ) note 1 t sik1 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 30 pf, r b = 5.5 k ? 479 479 479 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? 19 19 19 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 19 19 19 ns sip hold time (from sckp ? ) note 1 t ksi1 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 30 pf, r b = 5.5 k ? 19 19 19 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? 100 100 100 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 195 195 195 ns delay time from sckp ? to sop output note 1 t kso1 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 30 pf, r b = 5.5 k ? 483 483 483 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. 2. use it with ev dd0 ? v b . caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (when 20- to 52-pin products)/ev dd tolerance (when 64- to 128-pin pr oducts)) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port outp ut mode register g (pomg). for v ih and v il , see the dc characteristics wit h ttl input buffer selected. (remarks are listed on the page after the next page.)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 99 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (8) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (3/3) (t a = ? 40 to +85 ? c, 1.8 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? 44 110 110 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 44 110 110 ns sip setup time (to sckp ? ) note 1 t sik1 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 30 pf, r b = 5.5 k ? 110 110 110 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? 19 19 19 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 19 19 19 ns sip hold time (from sckp ? ) note 1 t ksi1 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 30 pf, r b = 5.5 k ? 19 19 19 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? 25 25 25 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 25 25 25 ns delay time from sckp ? to sop output note 1 t kso1 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 30 pf, r b = 5.5 k ? 25 25 25 ns notes 1. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. use it with ev dd0 ? v b . caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (when 20- to 52-pin products)/ev dd tolerance (when 64- to 128-pin pr oducts)) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port outp ut mode register g (pomg). for v ih and v il , see the dc characteristics wit h ttl input buffer selected. (remarks are listed on the next page.)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 100 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 csi mode connection diagram (during communication at different potential) v b r b sckp sop sck si user device sip so v b r b rl78 microcontroller remarks 1. r b [ ? ]:communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00, 01, 10, 20, 30, 31), m: unit number , n: channel number (mn = 00, 01, 02, 10, 12, 13), g: pim and pom number (g = 0, 1, 4, 5, 8, 14) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) 4. csi01 of 48-, 52-, 64-pin products, and csi11 and cs i21 cannot communicate at different potential. use other csi for communication at different potential.
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 101 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp remarks 1. p: csi number (p = 00, 01, 10, 20, 30, 31), m: unit number, n: channel number (mn = 00, 01, 02, 10, 12, 13), g: pim and pom number (g = 0, 1, 4, 5, 8, 14) 2. csi01 of 48-, 52-, 64-pin products, and csi11 and cs i21 cannot communicate at different potential. use other csi for communication at different potential.
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 102 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (9) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (slave mode, sckp... external clock input) (t a = ? 40 to +85 ? c, 1.8 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (1/2) hs (high- speed main) mode ls (low-speed main) mode lv (low-voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit 24 mhz < f mck 14/ f mck ? ? ns 20 mhz < f mck ? 24 mhz 12/ f mck ? ? ns 8 mhz < f mck ? 20 mhz 10/ f mck ? ? ns 4 mhz < f mck ? 8 mhz 8/f mck 16/ f mck ? ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v f mck ? 4 mhz 6/f mck 10/ f mck 10/ f mck ns 24 mhz < f mck 20/ f mck ? ? ns 20 mhz < f mck ? 24 mhz 16/ f mck ? ? ns 16 mhz < f mck ? 20 mhz 14/ f mck ? ? ns 8 mhz < f mck ? 16 mhz 12/ f mck ? ? ns 4 mhz < f mck ? 8 mhz 8/f mck 16/ f mck ? ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v f mck ? 4 mhz 6/f mck 10/ f mck 10/ f mck ns 24 mhz < f mck 48/ f mck ? ? ns 20 mhz < f mck ? 24 mhz 36/ f mck ? ? ns 16 mhz < f mck ? 20 mhz 32/ f mck ? ? ns 8 mhz < f mck ? 16 mhz 26/ f mck ? ? ns 4 mhz < f mck ? 8 mhz 16/ f mck 16/ f mck ? ns sckp cycle time note 1 t kcy2 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 f mck ? 4 mhz 10/ f mck 10/ f mck 10/ f mck ns (notes and caution are listed on the next page, and remarks are listed on the page after the next page.)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 103 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (9) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (slave mode, sckp... external clock input) (t a = ? 40 to +85 ? c, 1.8 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/2) hs (high- speed main) mode ls (low-speed main) mode lv (low-voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v t kcy2 /2 ? 12 t kcy2 /2 ? 50 t kcy2 /2 ? 50 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v t kcy2 /2 ? 18 t kcy2 /2 ? 50 t kcy2 /2 ? 50 ns sckp high-/low-level width t kh2 , t kl2 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 t kcy2 /2 ? 50 t kcy2 /2 ? 50 t kcy2 /2 ? 50 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v 1/f mck + 20 1/f mck + 30 1/f mck + 30 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v 1/f mck + 20 1/f mck + 30 1/f mck + 30 ns sip setup time (to sckp ? ) note 3 t sik2 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 1/f mck + 30 1/f mck + 30 1/f mck + 30 ns sip hold time (from sckp ? ) note 4 t ksi2 1/f mck + 31 1/f mck + 31 1/f mck + 31 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? 2/f mck + 120 2/f mck + 573 2/f mck + 573 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 2/f mck + 214 2/f mck + 573 2/f mck + 573 ns delay time from sckp ? to sop output note 5 t kso2 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 30 pf, r b = 5.5 k ? 2/f mck + 573 2/f mck + 573 2/f mck + 573 ns notes 1. transfer rate in the snooze mode : max. 1 mbps 2. use it with ev dd0 ? v b . 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 5. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (for the 20- to 52-pin products)/ev dd tolerance (for the 64- to 128-pin products)) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port outp ut mode register g (pomg). for v ih and v il , see the dc characteristics wit h ttl input buffer selected. (remarks are listed on the next page.)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 104 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 csi mode connection diagram (during communication at different potential) rl78 microcontroller sop sck si user device sip so v b r b sckp remarks 1. r b [ ? ]:communication line (sop) pull-up resistance, c b [f]: communication line (sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00, 01, 10, 20, 30, 31), m: un it number, n: channel number (mn = 00, 01, 02, 10, 12, 13), g: pim and pom number (g = 0, 1, 4, 5, 8, 14) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bi t of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00, 01, 02, 10, 12, 13)) 4. csi01 of 48-, 52-, 64-pin products, and csi11 and cs i21 cannot communicate at different potential. use other csi for communication at different potential.
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 105 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 csi mode serial transfer timi ng (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 sckp csi mode serial transfer timi ng (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 sckp remarks 1. p: csi number (p = 00, 01, 10, 20, 30, 31), m: unit number, n: channel number (mn = 00, 01, 02, 10, 12. 13), g: pim and pom number (g = 0, 1, 4, 5, 8, 14) 2. csi01 of 48-, 52-, 64-pin products, and csi11 and cs i21 cannot communicate at different potential. use other csi for communication at different potential.
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 106 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (10) communication at different potential (1.8 v, 2.5 v, 3 v) (simplified i 2 c mode) (1/2) (t a = ? 40 to +85 ? c, 1.8 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 50 pf, r b = 2.7 k ? 1000 note 1 300 note 1 300 note 1 khz 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 50 pf, r b = 2.7 k ? 1000 note 1 300 note 1 300 note 1 khz 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 100 pf, r b = 2.8 k ? 400 note 1 300 note 1 300 note 1 khz 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 100 pf, r b = 2.7 k ? 400 note 1 300 note 1 300 ote 1 khz sclr clock frequency f scl 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 100 pf, r b = 5.5 k ? 300 note 1 300 note 1 300 note 1 khz 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 50 pf, r b = 2.7 k ? 475 1550 1550 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 50 pf, r b = 2.7 k ? 475 1550 1550 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 100 pf, r b = 2.8 k ? 1150 1550 1550 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 100 pf, r b = 2.7 k ? 1150 1550 1550 ns hold time when sclr = ?l? t low 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 100 pf, r b = 5.5 k ? 1550 1550 1550 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 50 pf, r b = 2.7 k ? 245 610 610 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 50 pf, r b = 2.7 k ? 200 610 610 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 100 pf, r b = 2.8 k ? 675 610 610 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 100 pf, r b = 2.7 k ? 600 610 610 ns hold time when sclr = ?h? t high 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 100 pf, r b = 5.5 k ? 610 610 610 ns
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 107 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (10) communication at different potentia l (1.8 v, 2.5 v, 3 v) (simplified i 2 c mode) (2/2) (t a = ? 40 to +85 ? c, 1.8 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 50 pf, r b = 2.7 k ? 1/f mck + 135 note 3 1/f mck + 190 note 3 1/f mck + 190 note 3 khz 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 50 pf, r b = 2.7 k ? 1/f mck + 135 note 3 1/f mck + 190 note 3 1/f mck + 190 note 3 khz 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 100 pf, r b = 2.8 k ? 1/f mck + 190 note 3 1/f mck + 190 note 3 1/f mck + 190 note 3 khz 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 100 pf, r b = 2.7 k ? 1/f mck + 190 note 3 1/f mck + 190 note 3 1/f mck + 190 note 3 khz data setup time (reception) t su:dat 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 100 pf, r b = 5.5 k ? 1/f mck + 190 note 3 1/f mck + 190 note 3 1/f mck + 190 note 3 khz 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 50 pf, r b = 2.7 k ? 0 305 0 305 0 305 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 50 pf, r b = 2.7 k ? 0 305 0 305 0 305 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 100 pf, r b = 2.8 k ? 0 355 0 355 0 355 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 100 pf, r b = 2.7 k ? 0 355 0 355 0 355 ns data hold time (transmission) t hd:dat 1.8 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 100 pf, r b = 5.5 k ? 0 405 0 405 0 405 ns notes 1. the value must also be equal to or less than f mck /4. 2. use it with ev dd0 ? v b . 3. set the f mck value to keep the hold time of sclr = "l" and sclr = "h". caution select the ttl input buffer and the n-ch open drain output (v dd tolerance (for the 20- to 52-pin products)/ev dd tolerance (for the 64- to 128-pin product s)) mode for the sdar pin and the n-ch open drain output (v dd tolerance (for the 20- to 52-pin products)/ev dd tolerance (for the 64- to 128- pin products)) mode for the sclr pin by using port inpu t mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics wit h ttl input buffer selected. ( remarks are listed on the next page.)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 108 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 simplified i 2 c mode connection diagram (during communication at different potential) sdar sclr sda scl user device v b r b v b r b rl78 microcontroller simplified i 2 c mode serial transfer timing (during communication at different potential) sdar t low t high t hd:dat sclr t su:dat 1/f scl remarks 1. r b [ ? ]:communication line (sdar, sclr) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance, v b [v]: communication line voltage 2. r: iic number (r = 00, 01, 10, 20, 30, 31), g: pim, pom number (g = 0, 1, 4, 5, 8, 14) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00, 01, 02, 10, 12, 13)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 109 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 2.5.2 serial interface iica (1) i 2 c standard mode (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit 2.7 v ? ev dd0 ? 5.5 v 0 100 0 100 0 100 khz 1.8 v ? ev dd0 ? 5.5 v 0 100 0 100 0 100 khz 1.7 v ? ev dd0 ? 5.5 v 0 100 0 100 0 100 khz scla0 clock frequency f scl standard mode: f clk ? 1 mhz 1.6 v ? ev dd0 ? 5.5 v ? 0 100 0 100 khz 2.7 v ? ev dd0 ? 5.5 v 4.7 4.7 4.7 ? s 1.8 v ? ev dd0 ? 5.5 v 4.7 4.7 4.7 ? s 1.7 v ? ev dd0 ? 5.5 v 4.7 4.7 4.7 ? s setup time of restart condition t su:sta 1.6 v ? ev dd0 ? 5.5 v ? 4.7 4.7 ? s 2.7 v ? ev dd0 ? 5.5 v 4.0 4.0 4.0 ? s 1.8 v ? ev dd0 ? 5.5 v 4.0 4.0 4.0 ? s 1.7 v ? ev dd0 ? 5.5 v 4.0 4.0 4.0 ? s hold time note 1 t hd:sta 1.6 v ? ev dd0 ? 5.5 v ? 4.0 4.0 ? s 2.7 v ? ev dd0 ? 5.5 v 4.7 4.7 4.7 ? s 1.8 v ? ev dd0 ? 5.5 v 4.7 4.7 4.7 ? s 1.7 v ? ev dd0 ? 5.5 v 4.7 4.7 4.7 ? s hold time when scla0 = ?l? t low 1.6 v ? ev dd0 ? 5.5 v ? 4.7 4.7 ? s 2.7 v ? ev dd0 ? 5.5 v 4.0 4.0 4.0 ? s 1.8 v ? ev dd0 ? 5.5 v 4.0 4.0 4.0 ? s 1.7 v ? ev dd0 ? 5.5 v 4.0 4.0 4.0 ? s hold time when scla0 = ?h? t high 1.6 v ? ev dd0 ? 5.5 v ? 4.0 4.0 ? s 2.7 v ? ev dd0 ? 5.5 v 250 250 250 ns 1.8 v ? ev dd0 ? 5.5 v 250 250 250 ns 1.7 v ? ev dd0 ? 5.5 v 250 250 250 ns data setup time (reception) t su:dat 1.6 v ? ev dd0 ? 5.5 v ? 250 250 ns 2.7 v ? ev dd0 ? 5.5 v 0 3.45 0 3.45 0 3.45 ? s 1.8 v ? ev dd0 ? 5.5 v 0 3.45 0 3.45 0 3.45 ? s 1.7 v ? ev dd0 ? 5.5 v 0 3.45 0 3.45 0 3.45 ? s data hold time (transmission) note 2 t hd:dat 1.6 v ? ev dd0 ? 5.5 v ? 0 3.45 0 3.45 ? s 2.7 v ? ev dd0 ? 5.5 v 4.0 4.0 4.0 ? s 1.8 v ? ev dd0 ? 5.5 v 4.0 4.0 4.0 ? s 1.7 v ? ev dd0 ? 5.5 v 4.0 4.0 4.0 ? s setup time of stop condition t su:sto 1.6 v ? ev dd0 ? 5.5 v ? 4.0 4.0 ? s 2.7 v ? ev dd0 ? 5.5 v 4.7 4.7 4.7 ? s 1.8 v ? ev dd0 ? 5.5 v 4.7 4.7 4.7 ? s 1.7 v ? ev dd0 ? 5.5 v 4.7 4.7 4.7 ? s bus-free time t buf 1.6 v ? ev dd0 ? 5.5 v ? 4.7 4.7 ? s (notes , caution and remark are listed on the next page.)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 110 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. caution the values in the above tabl e are applied even when bit 2 (pior2) in the peripheral i/o redirection register (pior) is 1. at this time, the pin characteristics (i oh1 , i ol1 , v oh1 , v ol1 ) must satisfy the values in the redir ect destination. remark the maximum value of cb (communication line capa citance) and the value of rb (communication line pull-up resistor) at that time in each mode are as follows. standard mode: c b = 400 pf, r b = 2.7 k ?
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 111 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (2) i 2 c fast mode (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit 2.7 v ? ev dd0 ? 5.5 v 0 400 0 400 0 400 khz scla0 clock frequency f scl fast mode: f clk ? 3.5 mhz 1.8 v ? ev dd0 ? 5.5 v 0 400 0 400 0 400 khz 2.7 v ? ev dd0 ? 5.5 v 0.6 0.6 0.6 ? s setup time of restart condition t su:sta 1.8 v ? ev dd0 ? 5.5 v 0.6 0.6 0.6 ? s 2.7 v ? ev dd0 ? 5.5 v 0.6 0.6 0.6 ? s hold time note 1 t hd:sta 1.8 v ? ev dd0 ? 5.5 v 0.6 0.6 0.6 ? s 2.7 v ? ev dd0 ? 5.5 v 1.3 1.3 1.3 ? s hold time when scla0 = ?l? t low 1.8 v ? ev dd0 ? 5.5 v 1.3 1.3 1.3 ? s 2.7 v ? ev dd0 ? 5.5 v 0.6 0.6 0.6 ? s hold time when scla0 = ?h? t high 1.8 v ? ev dd0 ? 5.5 v 0.6 0.6 0.6 ? s 2.7 v ? ev dd0 ? 5.5 v 100 100 100 ? s data setup time (reception) t su:dat 1.8 v ? ev dd0 ? 5.5 v 100 100 100 ? s 2.7 v ? ev dd0 ? 5.5 v 0 0.9 0 0.9 0 0.9 ? s data hold time (transmission) note 2 t hd:dat 1.8 v ? ev dd0 ? 5.5 v 0 0.9 0 0.9 0 0.9 ? s 2.7 v ? ev dd0 ? 5.5 v 0.6 0.6 0.6 ? s setup time of stop condition t su:sto 1.8 v ? ev dd0 ? 5.5 v 0.6 0.6 0.6 ? s 2.7 v ? ev dd0 ? 5.5 v 1.3 1.3 1.3 ? s bus-free time t buf 1.8 v ? ev dd0 ? 5.5 v 1.3 1.3 1.3 ? s notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. caution the values in the above tabl e are applied even when bit 2 (pior2) in the peripheral i/o redirection register (pior) is 1. at this time, the pin characteristics (i oh1 , i ol1 , v oh1 , v ol1 ) must satisfy the values in the redir ect destination. remark the maximum value of cb (communication line capa citance) and the value of rb (communication line pull-up resistor) at that time in each mode are as follows. fast mode: c b = 320 pf, r b = 1.1 k ?
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 112 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (3) i 2 c fast mode plus (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode parameter symbol conditions min. max. min. max. min. max. unit scla0 clock frequency f scl fast mode plus: f clk ? 10 mhz 2.7 v ? ev dd0 ? 5.5 v 0 1000 ? ? khz setup time of restart condition t su:sta 2.7 v ? ev dd0 ? 5.5 v 0.26 ? ? ? s hold time note 1 t hd:sta 2.7 v ? ev dd0 ? 5.5 v 0.26 ? ? ? s hold time when scla0 = ?l? t low 2.7 v ? ev dd0 ? 5.5 v 0.5 ? ? ? s hold time when scla0 = ?h? t high 2.7 v ? ev dd0 ? 5.5 v 0.26 ? ? ? s data setup time (reception) t su:dat 2.7 v ? ev dd0 ? 5.5 v 50 ? ? ? s data hold time (transmission) note 2 t hd:dat 2.7 v ? ev dd0 ? 5.5 v 0 0.45 ? ? ? s setup time of stop condition t su:sto 2.7 v ? ev dd0 ? 5.5 v 0.26 ? ? ? s bus-free time t buf 2.7 v ? ev dd0 ? 5.5 v 0.5 ? ? ? s notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. caution the values in the above tabl e are applied even when bit 2 (pior2) in the peripheral i/o redirection register (pior) is 1. at this time, the pin characteristics (i oh1 , i ol1 , v oh1 , v ol1 ) must satisfy the values in the redir ect destination. remark the maximum value of cb (communication line capa citance) and the value of rb (communication line pull-up resistor) at that time in each mode are as follows. fast mode plus: c b = 120 pf, r b = 1.1 k ? iica serial transfer timing t low t r t buf t high t f t hd:sta stop condition start condition restart condition stop condition t su:dat t su:sta t su:sto t hd:sta t hd:dat sclan sdaan remark n = 0, 1
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 113 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 2.6 analog characteristics 2.6.1 a/d converter characteristics classification of a/d converter characteristics reference voltage input channel reference voltage (+) = av refp reference voltage ( ? ) = av refm reference voltage (+) = v dd reference voltage ( ? ) = v ss reference voltage (+) = v bgr reference voltage ( ? ) = av refm ani0 to ani14 refer to 2.6.1 (1) . ani16 to ani26 refer to 2.6.1 (2) . refer to 2.6.1 (4) . internal reference voltage temperature sensor output voltage refer to 2.6.1 (1) . refer to 2.6.1 (3) . ? (1) when reference voltage (+)= av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target pin : ani2 to ani14, intern al reference voltage, and temperature sensor output voltage (t a = ? 40 to +85? c, 1.6 v ? av refp ? v dd ? 5.5 v, v ss = 0 v, reference voltage (+) = av refp , reference voltage (? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution res 8 10 bit 1.8 v ? av refp ? 5.5 v 1.2 ? 3.5 lsb overall error note 1 ainl 10-bit resolution av refp = v dd note 3 1.6 v ? av refp ? 5.5 v note 4 1.2 ? 7.0 lsb 3.6 v ? v dd ? 5.5 v 2.125 39 ? s 2.7 v ? v dd ? 5.5 v 3.1875 39 ? s 1.8 v ? v dd ? 5.5 v 17 39 ? s 10-bit resolution target pin: ani2 to ani14 1.6 v ? v dd ? 5.5 v 57 95 ? s 3.6 v ? v dd ? 5.5 v 2.375 39 ? s 2.7 v ? v dd ? 5.5 v 3.5625 39 ? s conversion time t conv 10-bit resolution target pin: internal reference voltage, and temperature sensor output voltage (hs (high-speed main) mode) 2.4 v ? v dd ? 5.5 v 17 39 ? s 1.8 v ? av refp ? 5.5 v ? 0.25 %fsr zero-scale error notes 1, 2 e zs 10-bit resolution av refp = v dd note 3 1.6 v ? av refp ? 5.5 v note 4 ? 0.50 %fsr 1.8 v ? av refp ? 5.5 v ? 0.25 %fsr full-scale error notes 1, 2 e fs 10-bit resolution av refp = v dd note 3 1.6 v ? av refp ? 5.5 v note 4 ? 0.50 %fsr 1.8 v ? av refp ? 5.5 v ? 2.5 lsb integral linearity error note 1 ile 10-bit resolution av refp = v dd note 3 1.6 v ? av refp ? 5.5 v note 4 ? 5.0 lsb 1.8 v ? av refp ? 5.5 v ? 1.5 lsb differential linearity error note 1 dle 10-bit resolution av refp = v dd note 3 1.6 v ? av refp ? 5.5 v note 4 ? 2.0 lsb ani2 to ani14 0 av refp v internal reference voltage (2.4 v ? v dd ? 5.5 v, hs (high-speed main) mode) v bgr note 5 v analog input voltage v ain temperature sensor output voltage (2.4 v ? v dd ? 5.5 v, hs (high-speed main) mode) v tmps25 note 5 v (notes are listed on the next page.)
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 114 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 notes 1. excludes quantization error ( ? 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. when av refp < v dd , the max. values are as follows. overall error: add ? 1.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add ? 0.05%fsr to the max. value when av refp = v dd . integral linearity error/ diffe rential linearity error: add ? 0.5 lsb to the max. value when av refp = v dd . 4. values when the conversi on time is set to 57 ? s (min.) and 95 ? s (max.). 5. refer to 2.6.2 temperature senso r/internal reference voltage characteristics .
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 115 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (2) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target pin : ani16 to ani26 (t a = ? 40 to +85? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, 1.6 v ? av refp ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution res 8 10 bit 1.8 v ? av refp ? 5.5 v 1.2 ?5.0 lsb overall error note 1 ainl 10-bit resolution ev dd0 = av refp = v dd notes 3, 4 1.6 v ? av refp ? 5.5 v note 5 1.2 ?8.5 lsb 3.6 v ? v dd ? 5.5 v 2.125 39 ? s 2.7 v ? v dd ? 5.5 v 3.1875 39 ? s 1.8 v ? v dd ? 5.5 v 17 39 ? s conversion time t conv 10-bit resolution target ani pin : ani16 to ani26 1.6 v ? v dd ? 5.5 v 57 95 ? s 1.8 v ? av refp ? 5.5 v ?0.35 %fsr zero-scale error notes 1, 2 e zs 10-bit resolution ev dd0 = av refp = v dd notes 3, 4 1.6 v ? av refp ? 5.5 v note 5 ?0.60 %fsr 1.8 v ? av refp ? 5.5 v ?0.35 %fsr full-scale error notes 1, 2 e fs 10-bit resolution ev dd0 = av refp = v dd notes 3, 4 1.6 v ? av refp ? 5.5 v note 5 ?0.60 %fsr 1.8 v ? av refp ? 5.5 v ?3.5 lsb integral linearity error note 1 ile 10-bit resolution ev dd0 = av refp = v dd notes 3, 4 1.6 v ? av refp ? 5.5 v note 5 ?6.0 lsb 1.8 v ? av refp ? 5.5 v ?2.0 lsb differential linearity error note 1 dle 10-bit resolution ev dd0 = av refp = v dd notes 3, 4 1.6 v ? av refp ? 5.5 v note 5 ?2.5 lsb analog input voltage v ain ani16 to ani26 0 av refp and ev dd0 v notes 1. excludes quantization error ( ? 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. when av refp < v dd , the max. values are as follows. overall error: add ? 1.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add ? 0.05%fsr to the max. value when av refp = v dd . integral linearity error/ diffe rential linearity error: add ? 0.5 lsb to the max. value when av refp = v dd . 4. when av refp < ev dd0 ? v dd , the max. values are as follows. overall error: add ? 4.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add ? 0.20%fsr to the max. value when av refp = v dd . integral linearity error/ diffe rential linearity error: add ? 2.0 lsb to the max. value when av refp = v dd . 5. when the conversion time is set to 57 ? s (min.) and 95 ? s (max.).
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 116 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (3) when reference voltage (+) = v dd (adrefp1 = 0, adrefp0 = 0), reference voltage ( ? ) = v ss (adrefm = 0), target pin : ani0 to ani14, ani16 to ani26, internal reference volt age, and temperature sensor output voltage (t a = ? 40 to +85 ? c, 1.6 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v, reference voltage (+) = v dd , reference voltage ( ? ) = v ss ) parameter symbol conditions min. typ. max. unit resolution res 8 10 bit 1.8 v ? v dd ? 5.5 v 1.2 ?7.0 lsb overall error note 1 ainl 10-bit resolution 1.6 v ? v dd ? 5.5 v note 3 1.2 ?10.5 lsb 3.6 v ? v dd ? 5.5 v 2.125 39 ? s 2.7 v ? v dd ? 5.5 v 3.1875 39 ? s 1.8 v ? v dd ? 5.5 v 17 39 ? s conversion time t conv 10-bit resolution target pin: ani0 to ani14, ani16 to ani26 1.6 v ? v dd ? 5.5 v 57 95 ? s 3.6 v ? v dd ? 5.5 v 2.375 39 ? s 2.7 v ? v dd ? 5.5 v 3.5625 39 ? s conversion time t conv 10-bit resolution target pin: internal reference voltage, and temperature sensor output voltage (hs (high-speed main) mode) 2.4 v ? v dd ? 5.5 v 17 39 ? s 1.8 v ? v dd ? 5.5 v ?0.60 %fsr zero-scale error notes 1, 2 e zs 10-bit resolution 1.6 v ? v dd ? 5.5 v note 3 ?0.85 %fsr 1.8 v ? v dd ? 5.5 v ?0.60 %fsr full-scale error notes 1, 2 e fs 10-bit resolution 1.6 v ? v dd ? 5.5 v note 3 ?0.85 %fsr 1.8 v ? v dd ? 5.5 v ?4.0 lsb integral linearity error note 1 ile 10-bit resolution 1.6 v ? v dd ? 5.5 v note 3 ?6.5 lsb 1.8 v ? v dd ? 5.5 v ?2.0 lsb differential linearity error note 1 dle 10-bit resolution 1.6 v ? v dd ? 5.5 v note 3 ?2.5 lsb ani0 to ani14 0 v dd v ani16 to ani26 0 ev dd0 v internal reference voltage (2.4 v ? v dd ? 5.5 v, hs (high-speed main) mode) v bgr note 4 v analog input voltage v ain temperature sensor output voltage (2.4 v ? v dd ? 5.5 v, hs (high-speed main) mode) v tmps25 note 4 v notes 1. excludes quantization error ( ? 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. when the conversion time is set to 57 ? s (min.) and 95 ? s (max.). 4. refer to 2.6.2 temperature senso r/internal reference voltage characteristics .
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 117 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (4) when reference voltage (+) = in ternal reference voltage (adrefp1 = 1, adrefp0 = 0), reference voltage (? ) = av refm /ani1 (adrefm = 1), target pin : ani0, ani2 to ani 14, ani16 to ani26 (t a = ? 40 to +85? c, 2.4 v ? v dd ? 5.5 v, 1.6 v ? ev dd0 = ev dd1 ? v dd , v ss = ev ss0 = ev ss1 = 0 v, reference voltage (+) = v bgr note 3 , reference voltage ( ? ) = av refm = 0 v note 4 , hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit resolution res 8 bit conversion time t conv 8-bit resolution 2.4 v ? v dd ? 5.5 v 17 39 ? s zero-scale error notes 1, 2 e zs 8-bit resolution 2.4 v ? v dd ? 5.5 v ?0.60 %fsr integral linearity error note 1 ile 8-bit resolution 2.4 v ? v dd ? 5.5 v ?2.0 lsb differential linearity error note 1 dle 8-bit resolution 2.4 v ? v dd ? 5.5 v ?1.0 lsb analog input voltage v ain 0 v bgr note 3 v notes 1. excludes quantization error ( ? 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. refer to 2.6.2 temperature senso r/internal reference voltage characteristics . 4. when reference voltage ( ? ) = v ss , the max. values are as follows. zero-scale error: add ? 0.35%fsr to the max. value when reference voltage ( ? ) = av refm . integral linearity error: add ? 0.5 lsb to the max. value when reference voltage ( ? ) = av refm . differential lineari ty error: add ? 0.2 lsb to the max. value when reference voltage ( ? ) = av refm .
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 118 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 2.6.2 temperature sensor/internal reference voltage characteristics (t a = ? 40 to +85 ? c, 2.4 v ? v dd ? 5.5 v, v ss = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit temperature sensor output voltage v tmps25 setting ads register = 80h, t a = +25 ? c 1.05 v internal reference voltage v bgr setting ads register = 81h 1.38 1.45 1.5 v temperature coefficient f vtmps temperature sensor that depends on the temperature ? 3.6 mv/ ? c operation stabilization wait time t amp 5 ? s 2.6.3 por circuit characteristics (t a = ? 40 to +85 ? c, v ss = 0 v) parameter symbol conditions min. typ. max. unit v por power supply rise time 1.47 1.51 1.55 v detection voltage v pdr power supply fall time 1.46 1.50 1.54 v minimum pulse width note t pw 300 ? s note minimum time required for a por reset when v dd exceeds below v pdr . this is also the minimum time required for a por reset from when v dd exceeds below 0.7 v to when v dd exceeds v por while stop mode is entered or the main system clock is stopped through se tting bit 0 (hiostop) and bit 7 (mstop) in the clock operation status control register (csc). t pw v por v pdr or 0.7 v supply voltage (v dd )
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 119 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 2.6.4 lvd circuit characteristics lvd detection voltage of reset mode and interrupt mode (t a = ? 40 to +85 ? c, v pdr ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit power supply rise time 3.98 4.06 4.14 v v lvd0 power supply fall time 3.90 3.98 4.06 v power supply rise time 3.68 3.75 3.82 v v lvd1 power supply fall time 3.60 3.67 3.74 v power supply rise time 3.07 3.13 3.19 v v lvd2 power supply fall time 3.00 3.06 3.12 v power supply rise time 2.96 3.02 3.08 v v lvd3 power supply fall time 2.90 2.96 3.02 v power supply rise time 2.86 2.92 2.97 v v lvd4 power supply fall time 2.80 2.86 2.91 v power supply rise time 2.76 2.81 2.87 v v lvd5 power supply fall time 2.70 2.75 2.81 v power supply rise time 2.66 2.71 2.76 v v lvd6 power supply fall time 2.60 2.65 2.70 v power supply rise time 2.56 2.61 2.66 v v lvd7 power supply fall time 2.50 2.55 2.60 v power supply rise time 2.45 2.50 2.55 v v lvd8 power supply fall time 2.40 2.45 2.50 v power supply rise time 2.05 2.09 2.13 v v lvd9 power supply fall time 2.00 2.04 2.08 v power supply rise time 1.94 1.98 2.02 v v lvd10 power supply fall time 1.90 1.94 1.98 v power supply rise time 1.84 1.88 1.91 v v lvd11 power supply fall time 1.80 1.84 1.87 v power supply rise time 1.74 1.77 1.81 v v lvd12 power supply fall time 1.70 1.73 1.77 v power supply rise time 1.64 1.67 1.70 v detection voltage supply voltage level v lvd13 power supply fall time 1.60 1.63 1.66 v minimum pulse width t lw 300 ? s detection delay time 300 ? s
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 120 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 lvd detection voltage of interrupt & reset mode (t a = ? 40 to +85 ? c, v pdr ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit v lvda0 v poc2 , v poc1 , v poc0 = 0, 0, 0, falling reset voltage 1.60 1.63 1.66 v rising release reset voltage 1.74 1.77 1.81 v v lvda1 lvis1, lvis0 = 1, 0 falling interrupt voltage 1.70 1.73 1.77 v rising release reset voltage 1.84 1.88 1.91 v v lvda2 lvis1, lvis0 = 0, 1 falling interrupt voltage 1.80 1.84 1.87 v rising release reset voltage 2.86 2.92 2.97 v v lvda3 lvis1, lvis0 = 0, 0 falling interrupt voltage 2.80 2.86 2.91 v v lvdb0 v poc2 , v poc1 , v poc0 = 0, 0, 1, falling reset voltage 1.80 1.84 1.87 v rising release reset voltage 1.94 1.98 2.02 v v lvdb1 lvis1, lvis0 = 1, 0 falling interrupt voltage 1.90 1.94 1.98 v rising release reset voltage 2.05 2.09 2.13 v v lvdb2 lvis1, lvis0 = 0, 1 falling interrupt voltage 2.00 2.04 2.08 v rising release reset voltage 3.07 3.13 3.19 v v lvdb3 lvis1, lvis0 = 0, 0 falling interrupt voltage 3.00 3.06 3.12 v v lvdc0 v poc2 , v poc1 , v poc0 = 0, 1, 0, falling reset voltage 2.40 2.45 2.50 v rising release reset voltage 2.56 2.61 2.66 v v lvdc1 lvis1, lvis0 = 1, 0 falling interrupt voltage 2.50 2.55 2.60 v rising release reset voltage 2.66 2.71 2.76 v v lvdc2 lvis1, lvis0 = 0, 1 falling interrupt voltage 2.60 2.65 2.70 v rising release reset voltage 3.68 3.75 3.82 v v lvdc3 lvis1, lvis0 = 0, 0 falling interrupt voltage 3.60 3.67 3.74 v v lvdd0 v poc2 , v poc1 , v poc0 = 0, 1, 1, falling reset voltage 2.70 2.75 2.81 v rising release reset voltage 2.86 2.92 2.97 v v lvdd1 lvis1, lvis0 = 1, 0 falling interrupt voltage 2.80 2.86 2.91 v rising release reset voltage 2.96 3.02 3.08 v v lvdd2 lvis1, lvis0 = 0, 1 falling interrupt voltage 2.90 2.96 3.02 v rising release reset voltage 3.98 4.06 4.14 v interrupt and reset mode v lvdd3 lvis1, lvis0 = 0, 0 falling interrupt voltage 3.90 3.98 4.06 v
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 121 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 2.6.5 power supply voltage rising slope characteristics (t a = ? 40 to +85 ? c, v ss = 0 v) parameter symbol conditions min. typ. max. unit power supply voltage rising slope s vdd 54 v/ms caution make sure to keep the internal reset state by the lvd circuit or an external reset until v dd reaches the operating voltage range shown in 2.4 ac characteristics. 2.7 ram data retention characteristics (t a = ? 40 to +85 ? c, v ss = 0 v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.46 note 5.5 v note this depends on the por detection voltage. for a falli ng voltage, data in ram ar e retained until the voltage reaches the level that triggers a po r reset but not once it reaches t he level at which a por reset is generated. v dd stop instruction execution standby release signal (interrupt request) stop mode ram data retention v dddr operation mode
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 122 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 2.8 flash memory programming characteristics (t a = ? 40 to +85 ? c, 1.8 v ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit cpu/peripheral hardware clock frequency f clk 1.8 v ? v dd ? 5.5 v 1 32 mhz number of code flash rewrites notes 1, 2, 3 retained for 20 years t a = 85? c 1,000 retained for 1 years t a = 25? c 1,000,000 retained for 5 years t a = 85? c 100,000 number of data flash rewrites notes 1, 2, 3 c erwr retained for 20 years t a = 85? c 10,000 times notes 1. 1 erase + 1 write after the er ase is regarded as 1 rewrite. the retaining years are until ne xt rewrite after the rewrite. 2. when using flash memory programmer and renesas electronics self programming library 3. these are the characteristics of t he flash memory and the results obtained from reliability testing by renesas electronics corporation. 2.9 dedicated flash memory programmer communication (uart) (t a = ? 40 to +85 ? c, 1.8 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit transfer rate during serial programming 115,200 1,000,000 bps
rl78/g13 2. electrical specifications (t a = -40 to +85 ? c) page 123 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 2.10 timing of entry to flash memory programming mode s (t a = ? 40 to +85 ? c, 1.8 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit time to complete the communication for the initial setting after the external reset is released t suinit por and lvd reset must be released before the external reset is released. 100 ms time to release the external reset after the tool0 pin is set to the low level t su por and lvd reset must be released before the external reset is released. 10 ? s ? time to hold the tool0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) t hd por and lvd reset must be released before the external reset is released. 1 ms reset tool0 <1> <2> <3> t suinit 723 s + t hd processing time t su <4> 1-byte data for setting mode <1> the low level is input to the tool0 pin. <2> the external reset is released (por and lvd reset must be released before the external reset is released.). <3> the tool0 pin is set to the high level. <4> setting of the flash memory programming mode by uart reception and complete the baud rate setting. remark t suinit : communication for the initial setti ng must be completed within 100 ms after the external reset is released during this period. t su : time to release the exte rnal reset after the tool0 pi n is set to the low level t hd : time to hold the tool0 pin at the low level a fter the external reset is released (excluding the processing time of the firmware to control the flash memory)
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 124 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 3. electrical specifications (g: industrial applications t a = -40 to +105 ? c) this chapter describes the following electrical specifications. target products g: industrial applications t a = ? 40 to +105c r5f100xxgxx cautions 1. the rl78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this func tion is used, and produ ct reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. 2. with products not provided with an ev dd0 , ev dd1 , ev ss0 , or ev ss1 pin, replace ev dd0 and ev dd1 with v dd , or replace ev ss0 and ev ss1 with v ss . 3. the pins mounted depend on the product. refer to 2.1 port function to 2.2.1 functions for each product. 4. please contact renesas electronics sales o ffice for derating of operation under t a = +85 ? c to +105 ? c. derating is the systematic reduction of load for the sake of improved reliability. remark when rl78/g13 is used in the range of t a = ? 40 to +85c, see chapter 2 electrical specifications (t a = ? 40 to +85c) . there are following differences between th e products "g: industrial applications (t a = ? 40 to +105 ? c)" and the products ?a: consumer applications, and d: industrial applications?. application parameter a: consumer applications, d: industrial applications g: industrial applications operating ambient temperature t a = -40 to +85? c t a = -40 to +105 ? c operating mode operating voltage range hs (high-speed main) mode: 2.7 v ? v dd ? 5.5 v@1 mhz to 32 mhz 2.4 v ? v dd ? 5.5 v@1 mhz to 16 mhz ls (low-speed main) mode: 1.8 v ? v dd ? 5.5 v@1 mhz to 8 mhz lv (low-voltage main) mode: 1.6 v ? v dd ? 5.5 v@1 mhz to 4 mhz hs (high-speed main) mode only: 2.7 v ? v dd ? 5.5 v@1 mhz to 32 mhz 2.4 v ? v dd ? 5.5 v@1 mhz to 16 mhz high-speed on-chip oscillator clock accuracy 1.8 v ? v dd ? 5.5 v ?1.0%@ t a = -20 to +85 ? c ?1.5%@ t a = -40 to -20 ? c 1.6 v ? v dd < 1.8 v ?5.0%@ t a = -20 to +85 ? c ?5.5%@ t a = -40 to -20 ? c 2.4 v ? v dd ? 5.5 v ?2.0%@ t a = +85 to +105? c ?1.0%@ t a = -20 to +85 ? c ?1.5%@ t a = -40 to -20 ? c serial array unit uart csi: f clk /2 (supporting 16 mbps), f clk /4 simplified i 2 c communication uart csi: f clk /4 simplified i 2 c communication iica normal mode fast mode fast mode plus normal mode fast mode voltage detector rise detection voltage: 1.67 v to 4.06 v (14 levels) fall detection voltage: 1.63 v to 3.98 v (14 levels) rise detection voltage: 2.61 v to 4.06 v (8 levels) fall detection voltage: 2.55 v to 3.98 v (8 levels) ( remark is listed on the next page.)
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 125 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 remark the electrical characteristics of t he products g: industrial applications (t a = -40 to +105 ? c) are different from those of the products ?a: cons umer applications, and d: industrial app lications?. for details, refer to 3.1 to 3.10. 3.1 absolute maximum ratings absolute maximum ratings (t a = 25 ? c) (1/2) parameter symbols conditions ratings unit v dd ?0.5 to +6.5 v ev dd0 , ev dd1 ev dd0 = ev dd1 ?0.5 to +6.5 v supply voltage ev ss0 , ev ss1 ev ss0 = ev ss1 ?0.5 to +0.3 v regc pin input voltage v iregc regc ?0.3 to +2.8 and ?0.3 to v dd +0.3 note 1 v v i1 p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p140 to p147 ?0.3 to ev dd0 +0.3 and ?0.3 to v dd +0.3 note 2 v v i2 p60 to p63 (n-ch open-drain) ?0.3 to +6.5 v input voltage v i3 p20 to p27, p121 to p124, p137, p150 to p156, exclk, exclks, reset ?0.3 to v dd +0.3 note 2 v v o1 p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p130, p140 to p147 ?0.3 to ev dd0 +0.3 and ?0.3 to v dd +0.3 note 2 v output voltage v o2 p20 to p27, p150 to p156 ?0.3 to v dd +0.3 note 2 v v ai1 ani16 to ani26 ?0.3 to ev dd0 +0.3 and ?0.3 to av ref (+) +0.3 notes 2, 3 v analog input voltage v ai2 ani0 to ani14 ?0.3 to v dd +0.3 and ?0.3 to av ref (+) +0.3 notes 2, 3 v notes 1. connect the regc pin to vss via a capacitor (0.47 to 1 ? f). this value regulates the absolute maximum rating of the regc pin. do not use this pin with voltage applied to it. 2. must be 6.5 v or lower. 3. do not exceed av ref (+) + 0.3 v in case of a/d conversion target pin . caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefor e the product must be used under conditions that ensure that the absolute maximum rati ngs are not exceeded. remarks 1. unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins. 2. av ref (+) : + side reference voltage of the a/d converter. 3. v ss : reference voltage
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 126 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 absolute maximum ratings (t a = 25 ? c) (2/2) parameter symbols conditions ratings unit per pin p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p130, p140 to p147 ?40 ma p00 to p04, p07, p32 to p37, p40 to p47, p102 to p106, p120, p125 to p127, p130, p140 to p145 ?70 ma i oh1 total of all pins ?170 ma p05, p06, p10 to p17, p30, p31, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100, p101, p110 to p117, p146, p147 ?100 ma per pin ?0.5 ma output current, high i oh2 total of all pins p20 to p27, p150 to p156 ?2 ma per pin p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p130, p140 to p147 40 ma p00 to p04, p07, p32 to p37, p40 to p47, p102 to p106, p120, p125 to p127, p130, p140 to p145 70 ma i ol1 total of all pins 170 ma p05, p06, p10 to p17, p30, p31, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, p100, p101, p110 to p117, p146, p147 100 ma per pin 1 ma output current, low i ol2 total of all pins p20 to p27, p150 to p156 5 ma in normal operation mode operating ambient temperature t a in flash memory programming mode ?40 to +105 ? c storage temperature t stg ?65 to +150 ? c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefor e the product must be used under conditions that ensure that the absolute maximum rati ngs are not exceeded. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 127 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 3.2 oscillator characteristics 3.2.1 x1, xt1 oscillator characteristics (t a = ? 40 to +105 ? c, 2.4 v ? v dd ? 5.5 v, v ss = 0 v) parameter resonator conditions min. typ. max. unit 2.7 v ? v dd ? 5.5 v 1.0 20.0 mhz x1 clock oscillation frequency (f x ) note ceramic resonator/ crystal resonator 2.4 v ? v dd ? 2.7 v 1.0 16.0 mhz xt1 clock oscillation frequency (f x ) note crystal resonator 32 32.768 35 khz note indicates only permissible oscillator frequency ranges. re fer to ac characteristics for instruction execution time. request evaluation by the manufacturer of t he oscillator circuit mounted on a board to check the oscillator characteristics. caution since the cpu is started by the high-speed on-chip oscillator clock after a reset release, check the x1 clock oscillation stabilization time using th e oscillation stabilization time counter status register (ostc) by the user. de termine the oscillation stabilization time of the ostc register and the oscillation stabilization time select register (osts) after suffi ciently evaluating the oscillation stabilization time with the resonator to be used. remark when using the x1 oscillator and xt1 oscillator, refer to 5.4 system clock oscillator. 3.2.2 on-chip oscillator characteristics (t a = ? 40 to +105 ? c, 2.4 v ? v dd ? 5.5 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit high-speed on-chip oscillator clock frequency notes 1, 2 f ih 1 32 mhz ?20 to +85 ? c 2.4 v ? v dd ? 5.5 v ? 1.0 +1.0 % ?40 to ?20 ? c 2.4 v ? v dd ? 5.5 v ? 1.5 +1.5 % high-speed on-chip oscillator clock frequency accuracy +85 to +105 ? c 2.4 v ? v dd ? 5.5 v ? 2.0 +2.0 % low-speed on-chip oscillator clock frequency f il 15 khz low-speed on-chip oscillator clock frequency accuracy ? 15 +15 % notes 1. high-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000c2h/010c2h) and bits 0 to 2 of hocodiv register. 2. this indicates the oscillator characteristics only. refer to ac characteristics for instruction execution time.
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 128 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 3.3 dc characteristics 3.3.1 pin characteristics (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (1/5) items symbol conditions min. typ. max. unit per pin for p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p130, p140 to p147 2.4 v ? ev dd0 ? 5.5 v -3.0 note 2 ma 4.0 v ? ev dd0 ? 5.5 v -30.0 ma 2.7 v ? ev dd0 < 4.0 v ? 10.0 ma total of p00 to p04, p07, p32 to p37, p40 to p47, p102 to p106, p120, p125 to p127, p130, p140 to p145 (when duty ? 70% note 3 ) 2.4 v ? ev dd0 < 2.7 v ?5.0 ma 4.0 v ? ev dd0 ? 5.5 v -30.0 ma 2.7 v ? ev dd0 < 4.0 v ? 19.0 ma total of p05, p06, p10 to p17, p30, p31, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100, p101, p110 to p117, p146, p147 (when duty ? 70% note 3 ) 2.4 v ? ev dd0 < 2.7 v ?10.0 ma i oh1 total of all pins (when duty ? 70% note 3 ) 2.4 v ? ev dd0 ? 5.5 v -60.0 ma per pin for p20 to p27, p150 to p156 2,4 v ? v dd ? 5.5 v ?0.1 note 2 ma output current, high note 1 i oh2 total of all pins (when duty ? 70% note 3 ) 2.4 v ? v dd ? 5.5 v ?1.5 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from the ev dd0 , ev dd1 , v dd pins to an output pin. 2. do not exceed the total current value. 3. specification under conditions where the duty factor ? 70%. the output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changi ng the duty factor from 70% to n%). ? total output current of pins = (i oh 0.7)/(n 0.01) where n = 80% and i oh = ? 10.0 ma total output current of pins = ( ? 10.0 0.7)/(80 0.01) ? ? 8.7 ma however, the current that is allowed to flow into one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. caution p00, p02 to p04, p 10 to p15, p17, p43 to p45, p50, p52 to p55, p71, p74, p80 to p82, p96, and p142 to p144 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 129 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/5) items symbol conditions min. typ. max. unit per pin for p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p130, p140 to p147 8.5 note 2 ma per pin for p60 to p63 15.0 note 2 ma 4.0 v ? ev dd0 ? 5.5 v 40.0 ma 2.7 v ? ev dd0 < 4.0 v 15.0 ma total of p00 to p04, p07, p32 to p37, p40 to p47, p102 to p106, p120, p125 to p127, p130, p140 to p145 (when duty ? 70% note 3 ) 2.4 v ? ev dd0 < 2.7 v 9.0 ma 4.0 v ? ev dd0 ? 5.5 v 40.0 ma 2.7 v ? ev dd0 < 4.0 v 35.0 ma total of p05, p06, p10 to p17, p30, p31, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, p100, p101, p110 to p117, p146, p147 (when duty ? 70% note 3 ) 2,4 v ? ev dd0 < 2.7 v 20.0 ma i ol1 total of all pins (when duty ? 70% note 3 ) 80.0 ma per pin for p20 to p27, p150 to p156 0.4 note 2 ma output current, low note 1 i ol2 total of all pins (when duty ? 70% note 3 ) 2,4 v ? v dd ? 5.5 v 5.0 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from an output pin to the ev ss0 , ev ss1 and v ss pin. 2. do not exceed the total current value. 3. specification under conditions where the duty factor ? 70%. the output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changi ng the duty factor from 70% to n%). ? total output current of pins = (i ol 0.7)/(n 0.01) where n = 80% and i ol = 10.0 ma total output current of pi ns = (10.0 0.7)/(80 0.01) ? 8.7 ma however, the current that is allowed to flow into one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 130 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (3/5) items symbol conditions min. typ. max. unit v ih1 p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p140 to p147 normal input buffer 0.8ev dd0 ev dd0 v ttl input buffer 4.0 v ? ev dd0 ? 5.5 v 2.2 ev dd0 v ttl input buffer 3.3 v ? ev dd0 ? 4.0 v 2.0 ev dd0 v v ih2 p01, p03, p04, p10, p11, p13 to p17, p43, p44, p53 to p55, p80, p81, p142, p143 ttl input buffer 2.4 v ? ev dd0 ? 3.3 v 1.5 ev dd0 v v ih3 p20 to p27, p150 to p156 0.7v dd v dd v v ih4 p60 to p63 0.7ev dd0 6.0 v input voltage, high v ih5 p121 to p124, p137, exclk, exclks, reset 0.8v dd v dd v v il1 p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p140 to p147 normal input buffer 0 0.2ev dd0 v ttl input buffer 4.0 v ? ev dd0 ? 5.5 v 0 0.8 v ttl input buffer 3.3 v ? ev dd0 ? 4.0 v 0 0.5 v v il2 p01, p03, p04, p10, p11, p13 to p17, p43, p44, p53 to p55, p80, p81, p142, p143 ttl input buffer 2.4 v ? ev dd0 ? 3.3 v 0 0.32 v v il3 p20 to p27, p150 to p156 0 0.3v dd v v il4 p60 to p63 0 0.3ev dd0 v input voltage, low v il5 p121 to p124, p137, exclk, exclks, reset 0 0.2v dd v caution the maximum value of v ih of pins p00, p02 to p04, p10 to p15, p17, p43 to p45, p50, p52 to p55, p71, p74, p80 to p82, p96, and p142 to p144 is ev dd0 , even in the n-ch open-drain mode. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 131 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (4/5) items symbol conditions min. typ. max. unit 4.0 v ? ev dd0 ? 5.5 v, i oh1 = ? 3.0 ma ev dd0 ? 0.7 v 2.7 v ? ev dd0 ? 5.5 v, i oh1 = ? 2.0 ma ev dd0 ? 0.6 v v oh1 p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p130, p140 to p147 2.4 v ? ev dd0 ? 5.5 v, i oh1 = ? 1.5 ma ev dd0 ? 0.5 v output voltage, high v oh2 p20 to p27, p150 to p156 2.4 v ? v dd ? 5.5 v, i oh2 = ?100 ? a v dd ? 0.5 v 4.0 v ? ev dd0 ? 5.5 v, i ol1 = 8.5 ma 0.7 v 4.0 v ? ev dd0 ? 5.5 v, i ol1 = 3.0 ma 0.6 v 2.7 v ? ev dd0 ? 5.5 v, i ol1 = 1.5 ma 0.4 v v ol1 p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p130, p140 to p147 2.4 v ? ev dd0 ? 5.5 v, i ol1 = 0.6 ma 0.4 v v ol2 p20 to p27, p150 to p156 2.4 v ? v dd ? 5.5 v, i ol2 = 400 ? a 0.4 v 4.0 v ? ev dd0 ? 5.5 v, i ol3 = 15.0 ma 2.0 v 4.0 v ? ev dd0 ? 5.5 v, i ol3 = 5.0 ma 0.4 v 2.7 v ? ev dd0 ? 5.5 v, i ol3 = 3.0 ma 0.4 v output voltage, low v ol3 p60 to p63 2.4 v ? ev dd0 ? 5.5 v, i ol3 = 2.0 ma 0.4 v caution p00, p02 to p04, p10 to p15, p17, p43 to p45, p50, p52 to p55, p71, p74, p80 to p82, p96, and p142 to p144 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 132 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (5/5) items symbol conditions min. typ. max. unit i lih1 p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p140 to p147 v i = ev dd0 1 ? a i lih2 p20 to p27, p137, p150 to p156, reset v i = v dd 1 ? a in input port or external clock input 1 ? a input leakage current, high i lih3 p121 to p124 (x1, x2, xt1, xt2, exclk, exclks) v i = v dd in resonator connection 10 ? a i lil1 p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p140 to p147 v i = ev ss0 ?1 ? a i lil2 p20 to p27, p137, p150 to p156, reset v i = v ss ?1 ? a in input port or external clock input ?1 ? a input leakage current, low i lil3 p121 to p124 (x1, x2, xt1, xt2, exclk, exclks) v i = v ss in resonator connection ?10 ? a on-chip pll-up resistance r u p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p90 to p97, p100 to p106, p110 to p117, p120, p125 to p127, p140 to p147 v i = ev ss0 , in input port 10 20 100 k ? remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 133 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 3.3.2 supply current characteristics (1) flash rom: 16 to 64 kb of 20- to 64-pin products (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 ? v dd ? 5.5 v, v ss = ev ss0 = 0 v) (1/2) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 2.1 ma basic operatio n v dd = 3.0 v 2.1 ma v dd = 5.0 v 4.6 7.5 ma f ih = 32 mhz note 3 normal operatio n v dd = 3.0 v 4.6 7.5 ma v dd = 5.0 v 3.7 5.8 ma ? note 3 normal operatio n v dd = 3.0 v 3.7 5.8 ma v dd = 5.0 v 2.7 4.2 ma ? note 5 f ih = 16 mhz note 3 normal operatio n v dd = 3.0 v 2.7 4.2 ma square wave input 3.0 4.9 ma f mx = 20 mhz note 2 , v dd = 5.0 v normal operatio n resonator connection 3.2 5.0 ma square wave input 3.0 4.9 ma ? note 2 , v dd = 3.0 v normal operatio n resonator connection 3.2 5.0 ma square wave input 1.9 2.9 ma ? note 2 , v dd = 5.0 v normal operatio n resonator connection 1.9 2.9 ma square wave input 1.9 2.9 ma ? note 5 f mx = 10 mhz note 2 , v dd = 3.0 v normal operatio n resonator connection 1.9 2.9 ma square wave input 4.1 4.9 ? a f sub = 32.768 khz note 4 t a = ?40 ? c normal operatio n resonator connection 4.2 5.0 ? a square wave input 4.1 4.9 ? a f sub = 32.768 khz note 4 t a = +25 ? c normal operatio n resonator connection 4.2 5.0 ? a square wave input 4.2 5.5 ? a f sub = 32.768 khz note 4 t a = +50 ? c normal operatio n resonator connection 4.3 5.6 ? a square wave input 4.3 6.3 ? a f sub = 32.768 khz note 4 t a = +70 ? c normal operatio n resonator connection 4.4 6.4 ? a square wave input 4.6 7.7 ? a f sub = 32.768 khz note 4 t a = +85 ? c normal operation resonator connection 4.7 7.8 ? a square wave input 6.9 19.7 ? a supply current note 1 i dd1 operating mode subsystem clock operation f sub = 32.768 khz note 4 t a = +105 ? c normal operation resonator connection 7.0 19.8 ? a (notes and remarks are listed on the next page.)
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 134 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 notes 1. total current flowing into v dd and ev dd0 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 or v ss , ev ss0 . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d conver ter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the cu rrent flowing during data flash rewrite. 2. when high-speed on-chip oscillator and subsystem clock are stopped. 3. when high-speed system clock and subsystem clock are stopped. 4. when high-speed on-chip oscillator and high-spee d system clock are stopped. when amphs1 = 1 (ultra-low power consumption oscillation). however, not including the current flowing into the rtc, 12- bit interval timer, and watchdog timer. 5. relationship between operation voltage width, operation frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v ? v dd ? 5.5 v@1 mhz to 32 mhz 2.4 v ? v dd ? 5.5 v@1 mhz to 16 mhz remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation, temper ature condition of t he typ. value is t a = 25 ?c
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 135 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (1) flash rom: 16 to 64 kb of 20- to 64-pin products (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 ? v dd ? 5.5 v, v ss = ev ss0 = 0 v) (2/2) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 0.54 2.90 ma f ih = 32 mhz note 4 v dd = 3.0 v 0.54 2.90 ma v dd = 5.0 v 0.44 2.30 ma f ih = 24 mhz note 4 v dd = 3.0 v 0.44 2.30 ma v dd = 5.0 v 0.40 1.70 ma hs (high- speed main) mode note 7 f ih = 16 mhz note 4 v dd = 3.0 v 0.40 1.70 ma square wave input 0.28 1.90 ma f mx = 20 mhz note 3 , v dd = 5.0 v resonator connection 0.45 2.00 ma square wave input 0.28 1.90 ma f mx = 20 mhz note 3 , v dd = 3.0 v resonator connection 0.45 2.00 ma square wave input 0.19 1.02 ma f mx = 10 mhz note 3 , v dd = 5.0 v resonator connection 0.26 1.10 ma square wave input 0.19 1.02 ma hs (high- speed main) mode note 7 f mx = 10 mhz note 3 , v dd = 3.0 v resonator connection 0.26 1.10 ma square wave input 0.25 0.57 ? a f sub = 32.768 khz note 5 t a = ?40 ? c resonator connection 0.44 0.76 ? a square wave input 0.30 0.57 ? a f sub = 32.768 khz note 5 t a = +25 ? c resonator connection 0.49 0.76 ? a square wave input 0.37 1.17 ? a f sub = 32.768 khz note 5 t a = +50 ? c resonator connection 0.56 1.36 ? a square wave input 0.53 1.97 ? a f sub = 32.768 khz note 5 t a = +70 ? c resonator connection 0.72 2.16 ? a square wave input 0.82 3.37 ? a f sub = 32.768 khz note 5 t a = +85 ? c resonator connection 1.01 3.56 ? a square wave input 3.01 15.37 ? a i dd2 note 2 halt mode subsystem clock operation f sub = 32.768 khz note 5 t a = +105 ? c resonator connection 3.20 15.56 ? a t a = ?40 ? c 0.18 0.50 ? a t a = +25 ? c 0.23 0.50 ? a t a = +50 ? c 0.30 1.10 ? a t a = +70 ? c 0.46 1.90 ? a t a = +85 ? c 0.75 3.30 ? a supply current note 1 i dd3 note 6 stop mode note 8 t a = +105 ? c 2.94 15.30 ? a (notes and remarks are listed on the next page.)
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 136 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 notes 1. total current flowing into v dd and ev dd0 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 or v ss , ev ss0 . the values below the max. column include the peripheral operation current. however, not incl uding the current flowing into the a/d converter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the cu rrent flowing during data flash rewrite. 2. during halt instruction execution by flash memory. 3. when high-speed on-chip oscillator and subsystem clock are stopped. 4. when high-speed system clock and subsystem clock are stopped. 5. when high-speed on-chip oscillator and high-spee d system clock are stopped. when rtclpc = 1 and setting ultra-low current consumption (amphs1 = 1). the current flowing into the rtc is included. however, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. not including the current flowing into the rt c, 12-bit interval timer, and watchdog timer. 7. relationship between operation voltage width, operat ion frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v ? v dd ? 5.5 v@1 mhz to 32 mhz 2.4 v ? v dd ? 5.5 v@1 mhz to 16 mhz 8. regarding the value for current operate the subsystem cl ock in stop mode, refer to that in halt mode. remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation and stop mode, temperature condition of the typ. value is t a = 25?c
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 137 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (2) flash rom: 96 to 256 kb of 30- to 100-pin products (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (1/2) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 2.3 ma basic operatio n v dd = 3.0 v 2.3 ma v dd = 5.0 v 5.2 9.2 ma f ih = 32 mhz note 3 normal operatio n v dd = 3.0 v 5.2 9.2 ma v dd = 5.0 v 4.1 7.0 ma ? note 3 normal operatio n v dd = 3.0 v 4.1 7.0 ma v dd = 5.0 v 3.0 5.0 ma ? note 5 f ih = 16 mhz note 3 normal operatio n v dd = 3.0 v 3.0 5.0 ma square wave input 3.4 5.9 ma f mx = 20 mhz note 2 , v dd = 5.0 v normal operatio n resonator connection 3.6 6.0 ma square wave input 3.4 5.9 ma ? note 2 , v dd = 3.0 v normal operatio n resonator connection 3.6 6.0 ma square wave input 2.1 3.5 ma ? note 2 , v dd = 5.0 v normal operatio n resonator connection 2.1 3.5 ma square wave input 2.1 3.5 ma ? note 5 f mx = 10 mhz note 2 , v dd = 3.0 v normal operatio n resonator connection 2.1 3.5 ma square wave input 4.8 5.9 ? a f sub = 32.768 khz note 4 t a = ?40 ? c normal operatio n resonator connection 4.9 6.0 ? a square wave input 4.9 5.9 ? a f sub = 32.768 khz note 4 t a = +25 ? c normal operatio n resonator connection 5.0 6.0 ? a square wave input 5.0 7.6 ? a f sub = 32.768 khz note 4 t a = +50 ? c normal operatio n resonator connection 5.1 7.7 ? a square wave input 5.2 9.3 ? a f sub = 32.768 khz note 4 t a = +70 ? c normal operatio n resonator connection 5.3 9.4 ? a square wave input 5.7 13.3 ? a f sub = 32.768 khz note 4 t a = +85 ? c normal operatio n resonator connection 5.8 13.4 ? a square wave input 10.0 46.0 ? a supply current note 1 i dd1 operating mode subsystem clock operation f sub = 32.768 khz note 4 t a = +105 ? c normal operatio n resonator connection 10.0 46.0 ? a (notes and remarks are listed on the next page.)
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 138 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 notes 1. total current flowing into v dd , ev dd0 , and ev dd1 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 , and ev dd1 , or v ss , ev ss0 , and ev ss1 . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d converter, lvd circuit, i/o port, and on-chip pull- up/pull-down resistors and the current flowing during data flash rewrite. 2. when high-speed on-chip oscillator and subsystem clock are stopped. 3. when high-speed system clock and subsystem clock are stopped. 4. when high-speed on-chip oscillator and high-sp eed system clock are stopped. when amphs1 = 1 (ultra-low power consumption oscillation). however, not including the current flowing into the 12-bit interval timer and watchdog timer. 5. relationship between operation voltage width, operat ion frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v ? v dd ? 5.5 v@1 mhz to 32 mhz 2.4 v ? v dd ? 5.5 v@1 mhz to 16 mhz remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation, temper ature condition of t he typ. value is t a = 25 ?c
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 139 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (2) flash rom: 96 to 256 kb of 30- to 100-pin products (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/2) (notes and remarks are listed on the next page.) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 0.62 3.40 ma f ih = 32 mhz note 4 v dd = 3.0 v 0.62 3.40 ma v dd = 5.0 v 0.50 2.70 ma f ih = 24 mhz note 4 v dd = 3.0 v 0.50 2.70 ma v dd = 5.0 v 0.44 1.90 ma hs (high- speed main) mode note 7 f ih = 16 mhz note 4 v dd = 3.0 v 0.44 1.90 ma square wave input 0.31 2.10 ma f mx = 20 mhz note 3 , v dd = 5.0 v resonator connection 0.48 2.20 ma square wave input 0.31 2.10 ma f mx = 20 mhz note 3 , v dd = 3.0 v resonator connection 0.48 2.20 ma square wave input 0.21 1.10 ma f mx = 10 mhz note 3 , v dd = 5.0 v resonator connection 0.28 1.20 ma square wave input 0.21 1.10 ma hs (high- speed main) mode note 7 f mx = 10 mhz note 3 , v dd = 3.0 v resonator connection 0.28 1.20 ma square wave input 0.28 0.61 ? a f sub = 32.768 khz note 5 t a = ?40 ? c resonator connection 0.47 0.80 ? a square wave input 0.34 0.61 ? a f sub = 32.768 khz note 5 t a = +25 ? c resonator connection 0.53 0.80 ? a square wave input 0.41 2.30 ? a f sub = 32.768 khz note 5 t a = +50 ? c resonator connection 0.60 2.49 ? a square wave input 0.64 4.03 ? a f sub = 32.768 khz note 5 t a = +70 ? c resonator connection 0.83 4.22 ? a square wave input 1.09 8.04 ? a f sub = 32.768 khz note 5 t a = +85 ? c resonator connection 1.28 8.23 ? a square wave input 5.50 41.00 ? a i dd2 note 2 halt mode subsystem clock operation f sub = 32.768 khz note 5 t a = +105 ? c resonator connection 5.50 41.00 ? a t a = ?40 ? c 0.19 0.52 ? a t a = +25 ? c 0.25 0.52 ? a t a = +50 ? c 0.32 2.21 ? a t a = +70 ? c 0.55 3.94 ? a t a = +85 ? c 1.00 7.95 ? a supply current note 1 i dd3 note 6 stop mode note 8 t a = +105 ? c 5.00 40.00 ? a
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 140 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 notes 1. total current flowing into v dd , ev dd0 , and ev dd1 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 , and ev dd1 , or v ss , ev ss0 , and ev ss1 . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d converter, lvd circuit, i/o port, and on-chip pull- up/pull-down resistors and the current flowing during data flash rewrite. 2. during halt instruction execution by flash memory. 3. when high-speed on-chip oscillator and subsystem clock are stopped. 4. when high-speed system clock and subsystem clock are stopped. 5. when high-speed on-chip oscillator and high-spee d system clock are stopped. when rtclpc = 1 and setting ultra-low current consumption (amphs1 = 1). the current flowing into the rtc is included. however, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. not including the current flowing into the rt c, 12-bit interval timer, and watchdog timer. 7. relationship between operation voltage width, operat ion frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v ? v dd ? 5.5 v@1 mhz to 32 mhz 2.4 v ? v dd ? 5.5 v@1 mhz to 16 mhz 8. regarding the value for current operate the subsystem cl ock in stop mode, refer to that in halt mode. remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation and stop mode, temperature condition of the typ. value is t a = 25?c
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 141 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (3) peripheral functions ( common to all products) (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit low-speed on- chip oscillator operating current i fil note 1 0.20 ? a rtc operating current i rtc notes 1, 2, 3 0.02 ? a 12-bit interval timer operating current i it notes 1, 2, 4 0.02 ? a watchdog timer operating current i wdt notes 1, 2, 5 f il = 15 khz 0.22 ? a normal mode, av refp = v dd = 5.0 v 1.3 1.7 ma a/d converter operating current i adc notes 1, 6 when conversion at maximum speed low voltage mode, av refp = v dd = 3.0 v 0.5 0.7 ma a/d converter reference voltage current i adref note 1 75.0 ? a temperature sensor operating current i tmps note 1 75.0 ? a lvd operating current i lvd notes 1, 7 0.08 ? a self programming operating current i fsp notes 1, 9 2.50 12.20 ma bgo operating current i bgo notes 1, 8 2.50 12.20 ma the mode is performed note 10 0.50 1.10 ma adc operation the a/d conversion operations are performed, loe voltage mode, av refp = v dd = 3.0 v 1.20 2.04 ma snooze operating current i snoz note 1 csi/uart operation 0.70 1.54 ma notes 1. current flowing to the v dd . 2. when high speed on-chip oscillator and high-speed system clock are stopped. 3. current flowing only to the real-time clock (rtc) (e xcluding the operating current of the low-speed on- chip oscillator and the xt1 oscillator). the supply curr ent of the rl78 microcontro llers is the sum of the values of either i dd1 or i dd2 , and i rtc , when the real-time clock operates in operation mode or halt mode. when the low-speed on-chip o scillator is selected, i fil should be added. i dd2 subsystem clock operation includes the operational current of the real-time clock. 4. current flowing only to the 12-bit interval timer (e xcluding the operating current of the low-speed on-chip oscillator and the xt1 oscillator). the supply current of the rl78 mi crocontrollers is the sum of the values of either i dd1 or i dd2 , and i it , when the 12-bit interval timer operates in operation mode or halt mode. when the low-speed on-chi p oscillator is selected, i fil should be added. 5. current flowing only to the watchdog timer (inclu ding the operating current of the low-speed on-chip oscillator). the supply current of the rl78 is the sum of i dd1 , i dd2 or i dd3 and i wdt when the watchdog timer operates.
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 142 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 6. current flowing only to the a/d converter. the supply current of the rl78 microcontrollers is the sum of i dd1 or i dd2 and i adc when the a/d converter is in operation. 7. current flowing only to the lvd circuit. the supply cu rrent of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i lvd when the lvd circuit is in operation. 8. current flowing only during data flash rewrite. 9. current flowing only during self programming. 10. for shift time to the snooze mode, see 18.3.3 snooze mode in the rl78/g13 user?s manual. remarks 1. f il : low-speed on-chip oscillator clock frequency 2. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 3. f clk : cpu/peripheral hardware clock frequency 4. temperature condition of the typ. value is t a = 25 ?c
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 143 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 3.4 ac characteristics (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) items symbol conditions min. typ. max. unit 2.7 v ? v dd ? 5.5 v 0.03125 1 ? s main system clock (f main ) operation hs (high-speed main) mode 2.4 v ? v dd < 2.7 v 0.0625 1 ? s subsystem clock (f sub ) operation 2.4 v ? v dd ? 5.5 v 28.5 30.5 31.3 ? s 2.7 v ? v dd ? 5.5 v 0.03125 1 ? s instruction cycle (minimum instruction execution time) t cy in the self programming mode hs (high-speed main) mode 2.4 v ? v dd < 2.7 v 0.0625 1 ? s 2.7 v ? v dd ? 5.5 v 1.0 20.0 mhz f ex 2.4 v ? v dd < 2.7 v 1.0 16.0 mhz external system clock frequency f exs 32 35 khz 2.7 v ? v dd ? 5.5 v 24 ns t exh , t exl 2.4 v ? v dd < 2.7 v 30 ns external system clock input high- level width, low-level width t exhs , t exls 13.7 ? s ti00 to ti07, ti10 to ti17 input high-level width, low-level width t tih , t til 1/f mck +10 ns note 4.0 v ? ev dd0 ? 5.5 v 16 mhz 2.7 v ? ev dd0 < 4.0 v 8 mhz to00 to to07, to10 to to17 output frequency f to hs (high-speed main) mode 2.4 v ? ev dd0 < 2.7 v 4 mhz 4.0 v ? ev dd0 ? 5.5 v 16 mhz 2.7 v ? ev dd0 < 4.0 v 8 mhz pclbuz0, pclbuz1 output frequency f pcl hs (high-speed main) mode 2.4 v ? ev dd0 < 2.7 v 4 mhz intp0 2.4 v ? v dd ? 5.5 v 1 ? s interrupt input high-level width, low-level width t inth , t intl intp1 to intp11 2.4 v ? ev dd0 ? 5.5 v 1 ? s key interrupt input low-level width t kr kr0 to kr7 2.4 v ? ev dd0 ? 5.5 v 250 ns reset low-level width t rsl 10 ? s note the following conditions are required for low voltage interface when e vdd0 < v dd 2.4v ? ev dd0 < 2.7 v : min. 125 ns remark f mck : timer array unit operation clock frequency (operation clock to be set by the cksmn0, cksmn1 bits of timer mode register mn (tmrmn). m: unit number (m = 0, 1), n: channel number (n = 0 to 7))
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 144 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 minimum instruction execution time dur ing main system clock operation t cy vs v dd (hs (high-speed main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 0.01 2.4 0.03125 0.0625 0.05 when the high-speed on-chip oscillator clock is selected during self programming when high-speed system clock is selected supply voltage v dd [v] cycle time t cy [s] ac timing test points v ih /v oh v il /v ol test points v ih /v oh v il /v ol external system clock timing exclk/exclks 1/f ex / 1/f exs t exl / t exls t exh / t exhs
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 145 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 ti/to timing ti00 to ti07, ti10 to ti17 t til t tih to00 to to07, to10 to to17 1/f to interrupt request input timing intp0 to intp11 t intl t inth key interrupt input timing kr0 to kr7 t kr reset input timing reset t rsl
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 146 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 3.5 peripheral functions characteristics ac timing test points v ih /v oh v il /v ol test points v ih /v oh v il /v ol 3.5.1 serial array unit (1) during communication at same potential (uart mode) (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode parameter symbol conditions min. max. unit f mck /12 note 2 bps transfer rate note 1 theoretical value of the maximum transfer rate f clk = 32 mhz, f mck = f clk 2.6 mbps notes 1. transfer rate in the snooze mode is 4800 bps only. 2. the following conditions are required for low voltage interface when e vdd0 < v dd . 2.4 v ? ev dd0 < 2.7 v : max. 1.3 mbps caution select the normal input buffer for the rxdq pi n and the normal output mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). uart mode connection diagram (duri ng communication at same potential) rl78 microcontroller txdq rxdq rx tx user device uart mode bit width (dur ing communication at same potential) (reference) baud rate error tolerance high-/low-bit width 1/transfer rate txdq rxdq remarks 1. q: uart number (q = 0 to 3), g: pim and pom number (g = 0, 1, 8, 14) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13))
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 147 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (2) during communication at same potential (csi mode) (master mode, sckp... internal clock output) (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port ou tput mode register g (pomg). remarks 1. p: csi number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom numbers (g = 0, 1, 4, 5, 8, 14) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) hs (high-speed main) mode parameter symbol conditions min. max. unit 2.7 v ? ev dd0 ? 5.5 v 250 ns sckp cycle time t kcy1 t kcy1 ? 4/f clk 2.4 v ? ev dd0 ? 5.5 v 500 ns 4.0 v ? ev dd0 ? 5.5 v t kcy1 /2 ? 24 ns 2.7 v ? ev dd0 ? 5.5 v t kcy1 /2 ? 36 ns sckp high-/low-level width t kh1 , t kl1 2.4 v ? ev dd0 ? 5.5 v t kcy1 /2 ? 76 ns 4.0 v ? ev dd0 ? 5.5 v 66 ns 2.7 v ? ev dd0 ? 5.5 v 66 ns sip setup time (to sckp ? ) note 1 t sik1 2.4 v ? ev dd0 ? 5.5 v 113 ns sip hold time (from sckp ? ) note 2 t ksi1 38 ns delay time from sckp ? to sop output note 3 t kso1 c = 30 pf note 4 50 ns
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 148 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (3) during communication at same potential (csi mode) (slave m ode, sckp... external clock input) (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode parameter symbol conditions min. max. unit 20 mhz < f mck 16/f mck ns 4.0 v ? ev dd0 ? 5.5 v f mck ? 20 mhz 12/f mck ns 16 mhz < f mck 16/f mck ns 2.7 v ? ev dd0 ? 5.5 v f mck ? 16 mhz 12/f mck ns 16/f mck ns sckp cycle time note 5 t kcy2 2.4 v ? ev dd0 ? 5.5 v 12/f mck and 1000 ns 4.0 v ? ev dd0 ? 5.5 v t kcy2 /2 ? 14 ns 2.7 v ? ev dd0 ? 5.5 v t kcy2 /2 ? 16 ns sckp high-/low-level width t kh2 , t kl2 2.4 v ? ev dd0 ? 5.5 v t kcy2 /2 ? 36 ns 2.7 v ? ev dd0 ? 5.5 v 1/f mck +40 ns sip setup time (to sckp ? ) note 1 t sik2 2.4 v ? ev dd0 ? 5.5 v 1/f mck +60 ns sip hold time (from sckp ? ) note 2 t ksi2 2.4 v ? ev dd0 ? 5.5 v 1/f mck +62 ns 2.7 v ? ev dd0 ? 5.5 v 2/f mck +66 ns delay time from sckp ? to sop output note 3 t kso2 c = 30 pf note 4 2.4 v ? ev dd0 ? 5.5 v 2/f mck +113 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sop output lines. 5. transfer rate in the snooze mode : max. 1 mbps caution select the normal input buffer for the sip pi n and sckp pin and the normal output mode for the sop pin by using port input mode register g (pimg) and port out put mode register g (pomg). remarks 1. p: csi number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pi m number (g = 0, 1, 4, 5, 8, 14) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) csi mode connection diagram (during communication at same potential) rl78 microcontroller sckp sop sck si user device sip so
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 149 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 csi mode serial transfer timing (during communication at same potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy1, 2 t kl1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp csi mode serial transfer timing (during communication at same potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy1, 2 t kh1, 2 t kl1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp remarks 1. p: csi number (p = 00, 01, 10, 11, 20, 21, 30, 31) 2. m: unit number, n: channel number (mn = 00 to 03, 10 to 13)
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 150 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (4) during communication at sam e potential (simplified i 2 c mode) (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode parameter symbol conditions min. max. unit 2.7 v ? ev dd0 ? 5.5 v, c b = 50 pf, r b = 2.7 k ? 400 note1 khz sclr clock frequency f scl 2.4 v ? ev dd0 ? 5.5 v, c b = 100 pf, r b = 3 k ? 100 note1 khz 2.7 v ? ev dd0 ? 5.5 v, c b = 50 pf, r b = 2.7 k ? 1200 ns hold time when sclr = ?l? t low 2.4 v ? ev dd0 ? 5.5 v, c b = 100 pf, r b = 3 k ? 4600 ns 2.7 v ? ev dd0 ? 5.5 v, c b = 50 pf, r b = 2.7 k ? 1200 ns hold time when sclr = ?h? t high 2.4 v ? ev dd0 ? 5.5 v, c b = 100 pf, r b = 3 k ? 4600 ns 2.7 v ? ev dd0 ? 5.5 v, c b = 50 pf, r b = 2.7 k ? 1/f mck + 220 note2 ns data setup time (reception) t su:dat 2.4 v ? ev dd ? 5.5 v, c b = 100 pf, r b = 3 k ? 1/f mck + 580 note2 ns 2.7 v ? ev dd0 ? 5.5 v, c b = 50 pf, r b = 2.7 k ? 0 770 ns data hold time (transmission) t hd:dat 2.4 v ? ev dd0 ? 5.5 v, c b = 100 pf, r b = 3 k ? 0 1420 ns notes 1. the value must also be equal to or less than f mck /4. 2. set the f mck value to keep the hold time of sclr = "l" and sclr = "h". caution select the normal input buffer and the n-ch open drain output (v dd tolerance (for the 20- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the sdar pin and the normal output mode for the sclr pin by using port input mode register g (pimg) and port output mode register h (pomh). ( remarks are listed on the next page.)
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 151 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 simplified i 2 c mode mode connection diagram (dur ing communication at same potential) rl78 microcontroller sdar sclr sda scl user device v dd r b simplified i 2 c mode serial transfer timing (dur ing communication at same potential) sdar t low t high t hd:dat sclr t su:dat 1/f scl remarks 1. r b [ ? ]:communication line (sdar) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance 2. r: iic number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: pim number (g = 0, 1, 4, 5, 8, 14), h: pom number (g = 0, 1, 4, 5, 7 to 9, 14) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number (m = 0, 1), n: channel number (n = 0 to 3), mn = 00 to 03, 10 to 13)
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 152 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (5) communication at different potential (1 .8 v, 2.5 v, 3 v) (uart mode) (1/2) (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode parameter symbol conditions min. max. unit f mck /12 note 1 bps 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v theoretical value of the maximum transfer rate f clk = 32 mhz, f mck = f clk 2.6 mbps f mck /12 note 1 bps 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v theoretical value of the maximum transfer rate f clk = 32 mhz, f mck = f clk 2.6 mbps f mck /12 notes 1,2 bps transfer rate reception 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v theoretical value of the maximum transfer rate f clk = 32 mhz, f mck = f clk 2.6 mbps notes 1. transfer rate in the snooze mode is 4800 bps only. 2. the following conditions are required for low voltage interface when e vdd0 < v dd . 2.4 v ? ev dd0 < 2.7 v : max. 1.3 mbps caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance (for the 20- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the txdq pin by using port input mode register g (pimg) a nd port output mode regi ster g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remarks 1. v b [v]: communication line voltage 2. q: uart number (q = 0 to 3), g: pi m and pom number (g = 0, 1, 8, 14) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13) 4. uart2 cannot communicate at di fferent potential when bit 1 (pior 1) of peripheral i/o redirection register (pior) is 1.
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 153 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (5) communication at different potential (1 .8 v, 2.5 v, 3 v) (uart mode) (2/2) (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode parameter symbol conditions min. max. unit note 1 bps 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v theoretical value of the maximum transfer rate c b = 50 pf, r b = 1.4 k ? , v b = 2.7 v 2.6 note 2 mbps note 3 bps 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v theoretical value of the maximum transfer rate c b = 50 pf, r b = 2.7 k ? , v b = 2.3 v 1.2 note 4 mbps note 5 bps transfer rate transmission 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v theoretical value of the maximum transfer rate c b = 50 pf, r b = 5.5 k ? , v b = 1.6 v 0.43 note 6 mbps notes 1. the smaller maximum transfer rate derived by using f mck /12 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 4.0 v ? ev dd0 ? 5.5 v and 2.7 v ? v b ? 4.0 v 1 maximum transfer rate = [bps] { ? c b r b ln (1 ? 2.2 v b )} 3 1 transfer rate ? 2 ? { ? c b r b ln (1 ? 2.2 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical va lue of the relative difference betwee n the transmission and reception sides. 2. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 1 above to calculate the maxi mum transfer rate under conditions of the customer. 3. the smaller maximum transfer rate derived by using f mck /12 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v ? ev dd0 < 4.0 v and 2.4 v ? v b ? 2.7 v 1 maximum transfer rate = { ? c b r b ln (1 ? 2.0 v b )} 3 [bps] 1 transfer rate ? 2 ? { ? c b r b ln (1 ? 2.0 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical va lue of the relative difference betwee n the transmission and reception sides. 4. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 3 above to calculate the maxi mum transfer rate under conditions of the customer.
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 154 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 5. the smaller maximum transfer rate derived by using f mck /12 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.4 v ? ev dd0 < 3.3 v and 1.6 v ? v b ? 2.0 v 1 maximum transfer rate = [bps] { ? c b r b ln (1 ? 1.5 v b )} 3 1 transfer rate ? 2 ? { ? c b r b ln (1 ? 1.5 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical va lue of the relative difference betwee n the transmission and reception sides. 6. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 5 above to calculate the maxi mum transfer rate under conditions of the customer. caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance (for the 20- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. uart mode connection diagram (during communication at different potential) rl78 microcontroller txdq rxdq rx tx user device v b r b
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 155 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 uart mode bit width (during communication at different potential) (reference) txdq rxdq baud rate error tolerance baud rate error tolerance low-bit width high-/low-bit width high-bit width 1/transfer rate 1/transfer rate remarks 1. r b [ ? ]:communication line (txdq) pull-up resistance, c b [f]: communication line (txdq) load capacitance, v b [v]: communication line voltage 2. q: uart number (q = 0 to 3), g: pi m and pom number (g = 0, 1, 8, 14) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) 4. uart2 cannot communicate at different potential when bit 1 (pior1) of peripheral i/o redirection register (pior) is 1.
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 156 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (6) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (1/3) (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode parameter symbol conditions min. max. unit 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? 600 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 1000 ns sckp cycle time t kcy1 t kcy1 ? 4/f clk 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v, c b = 30 pf, r b = 5.5 k ? 2300 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? t kcy1 /2 ? 150 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? t kcy1 /2 ? 340 ns sckp high-level width t kh1 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v, c b = 30 pf, r b = 5.5 k ? t kcy1 /2 ? 916 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? t kcy1 /2 ? 24 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? t kcy1 /2 ? 36 ns sckp low-level width t kl1 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v, c b = 30 pf, r b = 5.5 k ? t kcy1 /2 ? 100 ns caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (for the 20- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin pr oducts)) mode for the sop pin and sckp pin by using port input mode register g (p img) and port output mode register g (pomg). for v ih and v il , see the dc characteristics wit h ttl input buffer selected. ( remarks are listed two pages after the next page.)
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 157 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (6) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (2/3) (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode parameter symbol conditions min. max. unit 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? 162 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 354 ns sip setup time (to sckp ? ) note t sik1 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v, c b = 30 pf, r b = 5.5 k ? 958 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? 38 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 38 ns sip hold time (from sckp ? ) note t ksi1 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v, c b = 30 pf, r b = 2.7 k ? 38 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? 200 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 390 ns delay time from sckp ? to sop output note t kso1 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v, c b = 30 pf, r b = 5.5 k ? 966 ns note when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (for the 20- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port outp ut mode register g (pomg). for v ih and v il , see the dc characteristics wit h ttl input buffer selected. ( remarks are listed on the page after the next page.)
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 158 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (6) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (3/3) (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode parameter symbol conditions min. max. unit 4.0 v ? ev dd ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? 88 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 88 ns sip setup time (to sckp ? ) note t sik1 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v, c b = 30 pf, r b = 5.5 k ? 220 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? 38 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 38 ns sip hold time (from sckp ? ) note t ksi1 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v, c b = 30 pf, r b = 5.5 k ? 38 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? 50 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 50 ns delay time from sckp ? to sop output note t kso1 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v, c b = 30 pf, r b = 5.5 k ? 50 ns note when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (for the 20- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port outp ut mode register g (pomg). for v ih and v il , see the dc characteristics wit h ttl input buffer selected. ( remarks are listed on the next page.)
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 159 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 csi mode connection diagram (during communication at different potential) v b r b sop sck si sip so v b r b rl78 microcontroller sckp user device remarks 1. r b [ ? ]:communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00, 01, 10, 20, 30, 31), m: un it number , n: channel number (mn = 00, 01, 02, 10, 12, 13), g: pim and pom number (g = 0, 1, 4, 5, 8, 14) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bi t of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) 4. csi01 of 48-, 52-, 64-pin products, and csi11 and cs i21 cannot communicate at different potential. use other csi for communication at different potential.
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 160 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp remarks 1. p: csi number (p = 00, 01, 10, 20, 30, 31), m: un it number (m = 00, 01, 02, 10, 12, 13), n: channel number (n = 0, 2), g: pim and pom num ber (g = 0, 1, 4, 5, 8, 14) 2. csi01 of 48-, 52-, 64-pin products, and csi11 and cs i21 cannot communicate at different potential. use other csi for communication at different potential.
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 161 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (7) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (slave mode, sckp... external clock input) (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode parameter symbol conditions min. max. unit 24 mhz < f mck 28/f mck ns 20 mhz < f mck ? 24 mhz 24/f mck ns 8 mhz < f mck ? 20 mhz 20/f mck ns 4 mhz < f mck ? 8 mhz 16/f mck ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v f mck ? 4 mhz 12/f mck ns 24 mhz < f mck 40/f mck ns 20 mhz < f mck ? 24 mhz 32/f mck ns 16 mhz < f mck ? 20 mhz 28/f mck ns 8 mhz < f mck ? 16 mhz 24/f mck ns 4 mhz < f mck ? 8 mhz 16/f mck ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v f mck ? 4 mhz 12/f mck ns 24 mhz < f mck 96/f mck ns 20 mhz < f mck ? 24 mhz 72/f mck ns 16 mhz < f mck ? 20 mhz 64/f mck ns 8 mhz < f mck ? 16 mhz 52/f mck ns 4 mhz < f mck ? 8 mhz 32/f mck ns sckp cycle time note 1 t kcy2 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v f mck ? 4 mhz 20/f mck ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v t kcy2 /2 ? 24 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v t kcy2 /2 ? 36 ns sckp high-/low-level width t kh2 , t kl2 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 t kcy2 /2 ? 100 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v 1/f mck + 40 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v 1/f mck + 40 ns sip setup time (to sckp ? ) note2 t sik2 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v 1/f mck + 60 ns sip hold time (from sckp ? ) note 3 t ksi2 1/f mck + 62 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 30 pf, r b = 1.4 k ? 2/f mck + 240 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 2/f mck + 428 ns delay time from sckp ? to sop output note 4 t kso2 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v c b = 30 pf, r b = 5.5 k ? 2/f mck + 1146 ns (notes , caution and remarks are listed on the next page.)
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 162 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 notes 1. transfer rate in the snooze mode : max. 1 mbps 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. caution select the ttl input buffer for the sip pi n and sckp pin and the n-ch open drain output (v dd tolerance (for the 20- to 52-pin products)/ev dd tolerance (for the 64- to 128-pin products)) mode for the sop pin by using port input mode regist er g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. csi mode connection diagram (during communication at different potential) rl78 microcontroller sckp sop sck si sip so v b r b user device remarks 1. r b [ ? ]:communication line (sop) pull-up resistance, c b [f]: communication line (sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00, 01, 10, 20, 30, 31), m: unit number (m = 0, 1), n: channel number (n = 00, 01, 02, 10, 12, 13), g: pim and pom number (g = 0, 1, 4, 5, 8, 14) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00, 01, 02, 10, 12, 13)) 4. csi01 of 48-, 52-, 64-pin products, and csi11 and cs i21 cannot communicate at different potential. use other csi for communication at different potential.
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 163 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 csi mode serial transfer timi ng (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 sckp csi mode serial transfer timi ng (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 sckp remarks 1. p: csi number (p = 00, 01, 10, 20, 30, 31), m: unit number, n: channel number (mn = 00, 01, 02, 10, 12. 13), g: pim and pom number (g = 0, 1, 4, 5, 8, 14) 2. csi01 of 48-, 52-, 64-pin products, and csi11 and cs i21 cannot communicate at different potential. use other csi for communication at different potential.
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 164 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (8) communication at different potential (1.8 v, 2.5 v, 3 v) (simplified i 2 c mode) (1/2) (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode parameter symbol conditions min. max. unit 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 50 pf, r b = 2.7 k ? 400 note 1 khz 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 50 pf, r b = 2.7 k ? 400 note 1 khz 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 100 pf, r b = 2.8 k ? 100 note 1 khz 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 100 pf, r b = 2.7 k ? 100 note 1 khz sclr clock frequency f scl 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v, c b = 100 pf, r b = 5.5 k ? 100 note 1 khz 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 50 pf, r b = 2.7 k ? 1200 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 50 pf, r b = 2.7 k ? 1200 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 100 pf, r b = 2.8 k ? 4600 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 100 pf, r b = 2.7 k ? 4600 ns hold time when sclr = ?l? t low 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v, c b = 100 pf, r b = 5.5 k ? 4650 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 50 pf, r b = 2.7 k ? 620 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 50 pf, r b = 2.7 k ? 500 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 100 pf, r b = 2.8 k ? 2700 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 100 pf, r b = 2.7 k ? 2400 ns hold time when sclr = ?h? t high 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v, c b = 100 pf, r b = 5.5 k ? 1830 ns (notes and caution are listed on the next page, and remarks are listed on the page after the next page.)
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 165 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (8) communication at different potential (1.8 v, 2.5 v, 3 v) (simplified i 2 c mode) (2/2) (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode parameter symbol conditions min. max. unit 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 50 pf, r b = 2.7 k ? 1/f mck + 340 note 2 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 50 pf, r b = 2.7 k ? 1/f mck + 340 note 2 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 100 pf, r b = 2.8 k ? 1/f mck + 760 note 2 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 100 pf, r b = 2.7 k ? 1/f mck + 760 note 2 ns data setup time (reception) t su:dat 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v, c b = 100 pf, r b = 5.5 k ? 1/f mck + 570 note 2 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 50 pf, r b = 2.7 k ? 0 770 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 50 pf, r b = 2.7 k ? 0 770 ns 4.0 v ? ev dd0 ? 5.5 v, 2.7 v ? v b ? 4.0 v, c b = 100 pf, r b = 2.8 k ? 0 1420 ns 2.7 v ? ev dd0 < 4.0 v, 2.3 v ? v b ? 2.7 v, c b = 100 pf, r b = 2.7 k ? 0 1420 ns data hold time (transmission) t hd:dat 2.4 v ? ev dd0 < 3.3 v, 1.6 v ? v b ? 2.0 v, c b = 100 pf, r b = 5.5 k ? 0 1215 ns notes 1. the value must also be equal to or less than f mck /4. 2. set the f mck value to keep the hold time of sclr = "l" and sclr = "h". caution select the ttl input buffer and the n-ch open drain output (v dd tolerance (for the 20- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin product s)) mode for the sdar pin and the n-ch open drain output (v dd tolerance (for the 20- to 52-pin products)/ev dd tolerance (for the 64- to 100- pin products)) mode for the sclr pin by using port inpu t mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics wit h ttl input buffer selected. ( remarks are listed on the next page.)
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 166 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 simplified i 2 c mode connection diagram (during communication at different potential) sdar sclr sda scl user device v b r b v b r b rl78 microcontroller simplified i 2 c mode serial transfer timing (during communication at different potential) sdar t low t high t hd:dat sclr t su:dat 1/f scl caution select the ttl input buffer and the n-ch open drain output (v dd tolerance (for the 20- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products )) mode for the sdar pin and the n-ch open drain output (v dd tolerance (for the 20- to 52-pin products)/ev dd tolerance (for the 64- to 100- pin products)) mode for the sclr pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics wit h ttl input buffer selected. remarks 1. r b [ ? ]:communication line (sdar, sclr) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance, v b [v]: communication line voltage 2. r: iic number (r = 00, 01, 10, 20, 30, 31), g: pim, pom number (g = 0, 1, 4, 5, 8, 14) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00, 01, 02, 10, 12, 13)
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 167 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 3.5.2 serial interface iica (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) hs (high-speed main) mode standard mode fast mode parameter symbol conditions min. max. min. max. unit fast mode: f clk ? 3.5 mhz ? ? 0 400 khz scla0 clock frequency f scl standard mode: f clk ? 1 mhz 0 100 ? ? khz setup time of restart condition t su:sta 4.7 0.6 ? s hold time note 1 t hd:sta 4.0 0.6 ? s hold time when scla0 = ?l? t low 4.7 1.3 ? s hold time when scla0 = ?h? t high 4.0 0.6 ? s data setup time (reception) t su:dat 250 100 ns data hold time (transmission) note 2 t hd:dat 0 3.45 0 0.9 ? s setup time of stop condition t su:sto 4.0 0.6 ? s bus-free time t buf 4.7 1.3 ? s notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. caution the values in the above tabl e are applied even when bit 2 (pior2) in the peripheral i/o redirection register (pior) is 1. at this time, the pin characteristics (i oh1 , i ol1 , v oh1 , v ol1 ) must satisfy the values in the redir ect destination. remark the maximum value of cb (communication line capa citance) and the value of rb (communication line pull-up resistor) at that time in each mode are as follows. standard mode: c b = 400 pf, r b = 2.7 k ? fast mode: c b = 320 pf, r b = 1.1 k ? iica serial transfer timing t r t buf t f t low t high t hd:sta stop condition start condition restart condition stop condition t su:dat t su:sta t su:sto t hd:sta t hd:dat sclan sdaan remark n = 0, 1
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 168 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 3.6 analog characteristics 3.6.1 a/d converter characteristics classification of a/d converter characteristics reference voltage input channel reference voltage (+) = av refp reference voltage ( ? ) = av refm reference voltage (+) = v dd reference voltage ( ? ) = v ss reference voltage (+) = v bgr reference voltage ( ? ) = av refm ani0 to ani14 refer to 3.6.1 (1) . ani16 to ani26 refer to 3.6.1 (2) . refer to 3.6.1 (4) . internal reference voltage temperature sensor output voltage refer to 3.6.1 (1) . refer to 3.6.1 (3) . ? (1) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target pin : ani2 to ani14, intern al reference voltage, and temperature sensor output voltage (t a = ? 40 to +105 ? c, 2.4 v ? av refp ? v dd ? 5.5 v, v ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution res 8 10 bit overall error note 1 ainl 10-bit resolution av refp = v dd note 3 2.4 v ? av refp ? 5.5 v 1.2 ?3.5 lsb 3.6 v ? v dd ? 5.5 v 2.125 39 ? s 2.7 v ? v dd ? 5.5 v 3.1875 39 ? s 10-bit resolution target pin: ani2 to ani14 2.4 v ? v dd ? 5.5 v 17 39 ? s 3.6 v ? v dd ? 5.5 v 2.375 39 ? s 2.7 v ? v dd ? 5.5 v 3.5625 39 ? s conversion time t conv 10-bit resolution target pin: internal reference voltage, and temperature sensor output voltage (hs (high-speed main) mode) 2.4 v ? v dd ? 5.5 v 17 39 ? s zero-scale error notes 1, 2 e zs 10-bit resolution av refp = v dd note 3 2.4 v ? av refp ? 5.5 v ?0.25 %fsr full-scale error notes 1, 2 e fs 10-bit resolution av refp = v dd note 3 2.4 v ? av refp ? 5.5 v ?0.25 %fsr integral linearity error note 1 ile 10-bit resolution av refp = v dd note 3 2.4 v ? av refp ? 5.5 v ?2.5 lsb differential linearity error note 1 dle 10-bit resolution av refp = v dd note 3 2.4 v ? av refp ? 5.5 v ?1.5 lsb ani2 to ani14 0 av refp v internal reference voltage output (2.4 v ? v dd ? 5.5 v, hs (high-speed main) mode) v bgr note 4 v analog input voltage v ain temperature sensor output voltage (2.4 v ? v dd ? 5.5 v, hs (high-speed main) mode) v tmps25 note 4 v (notes are listed on the next page.)
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 169 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 notes 1. excludes quantization error ( ? 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. when av refp < v dd , the max. values are as follows. overall error: add ? 1.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add ? 0.05%fsr to the max. value when av refp = v dd . integral linearity error/ diffe rential linearity error: add ? 0.5 lsb to the max. value when av refp = v dd . 4. refer to 3.6.2 temperature senso r/internal reference voltage characteristics .
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 170 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (2) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target pin : ani16 to ani26 (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, 2.4 v ? av refp ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution res 8 10 bit overall error note 1 ainl 10-bit resolution ev dd0 ? av refp = v dd notes 3, 4 2.4 v ? av refp ? 5.5 v 1.2 ?5.0 lsb 3.6 v ? v dd ? 5.5 v 2.125 39 ? s 2.7 v ? v dd ? 5.5 v 3.1875 39 ? s conversion time t conv 10-bit resolution target pin : ani16 to ani26 2.4 v ? v dd ? 5.5 v 17 39 ? s zero-scale error notes 1, 2 e zs 10-bit resolution ev dd0 ? av refp = v dd notes 3, 4 2.4 v ? av refp ? 5.5 v ?0.35 %fsr full-scale error notes 1, 2 e fs 10-bit resolution ev dd0 ? av refp = v dd notes 3, 4 2.4 v ? av refp ? 5.5 v ?0.35 %fsr integral linearity error note 1 ile 10-bit resolution ev dd0 ? av refp = v dd notes 3, 4 2.4 v ? av refp ? 5.5 v ?3.5 lsb differential linearity error note 1 dle 10-bit resolution ev dd0 ? av refp = v dd notes 3, 4 2.4 v ? av refp ? 5.5 v ?2.0 lsb analog input voltage v ain ani16 to ani26 0 av refp and ev dd0 v notes 1. excludes quantization error ( ? 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. when av refp < v dd , the max. values are as follows. overall error: add ? 1.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add ? 0.05%fsr to the max. value when av refp = v dd . integral linearity error/ diffe rential linearity error: add ? 0.5 lsb to the max. value when av refp = v dd . 4. when av refp < ev dd0 ? v dd , the max. values are as follows. overall error: add ? 4.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add ? 0.20%fsr to the max. value when av refp = v dd . integral linearity error/ diffe rential linearity error: add ? 2.0 lsb to the max. value when av refp = v dd .
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 171 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (3) when reference voltage (+) = v dd (adrefp1 = 0, adrefp0 = 0), reference voltage ( ? ) = v ss (adrefm = 0), target pin : ani0 to ani14, ani16 to ani26, internal reference vo ltage, and temperature sensor output voltage (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v, reference voltage (+) = v dd , reference voltage ( ? ) = v ss ) parameter symbol conditions min. typ. max. unit resolution res 8 10 bit overall error note 1 ainl 10-bit resolution 2.4 v ? v dd ? 5.5 v 1.2 ?7.0 lsb 3.6 v ? v dd ? 5.5 v 2.125 39 ? s 2.7 v ? v dd ? 5.5 v 3.1875 39 ? s 10-bit resolution target pin: ani0 to ani14, ani16 to ani26 2.4 v ? v dd ? 5.5 v 17 39 ? s 3.6 v ? v dd ? 5.5 v 2.375 39 ? s 2.7 v ? v dd ? 5.5 v 3.5625 39 ? s conversion time t conv 10-bit resolution target pin: internal reference voltage, and temperature sensor output voltage (hs (high-speed main) mode) 2.4 v ? v dd ? 5.5 v 17 39 ? s zero-scale error notes 1, 2 e zs 10-bit resolution 2.4 v ? v dd ? 5.5 v ?0.60 %fsr full-scale error notes 1, 2 e fs 10-bit resolution 2.4 v ? v dd ? 5.5 v ?0.60 %fsr integral linearity error note 1 ile 10-bit resolution 2.4 v ? v dd ? 5.5 v ?4.0 lsb differential linearity error note 1 dle 10-bit resolution 2.4 v ? v dd ? 5.5 v ?2.0 lsb ani0 to ani14 0 v dd v ani16 to ani26 0 ev dd0 v internal reference voltage output (2.4 v ? v dd ? 5.5 v, hs (high-speed main) mode) v bgr note 3 v analog input voltage v ain temperature sensor output voltage (2.4 v ? v dd ? 5.5 v, hs (high-speed main) mode) v tmps25 note 3 v notes 1. excludes quantization error ( ? 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. refer to 3.6.2 temperature senso r/internal reference voltage characteristics .
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 172 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 (4) when reference voltage (+) = internal reference voltage (adrefp1 = 1, adrefp0 = 0), reference voltage (? ) = av refm /ani1 (adrefm = 1), target pin : ani0, ani2 to ani 14, ani16 to ani26 (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v, reference voltage (+) = v bgr note 3 , reference voltage ( ? ) = av refm note 4 = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit resolution res 8 bit conversion time t conv 8-bit resolution 2.4 v ? v dd ? 5.5 v 17 39 ? s zero-scale error notes 1, 2 e zs 8-bit resolution 2.4 v ? v dd ? 5.5 v ?0.60 %fsr integral linearity error note 1 ile 8-bit resolution 2.4 v ? v dd ? 5.5 v ?2.0 lsb differential linearity error note 1 dle 8-bit resolution 2.4 v ? v dd ? 5.5 v ?1.0 lsb analog input voltage v ain 0 v bgr note 3 v notes 1. excludes quantization error ( ? 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. refer to 3.6.2 temperature senso r/internal reference voltage characteristics . 4. when reference voltage ( ? ) = v ss , the max. values are as follows. zero-scale error: add ? 0.35%fsr to the max. value when reference voltage ( ? ) = av refm . integral linearity error: add ? 0.5 lsb to the max. value when reference voltage ( ? ) = av refm . differential lineari ty error: add ? 0.2 lsb to the max. value when reference voltage ( ? ) = av refm . 3.6.2 temperature sensor/internal reference voltage characteristics (t a = ? 40 to +105 ? c, 2.4 v ? v dd ? 5.5 v, v ss = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit temperature sensor output voltage v tmps25 setting ads register = 80h, t a = +25 ? c 1.05 v internal reference voltage v bgr setting ads register = 81h 1.38 1.45 1.5 v temperature coefficient f vtmps temperature sensor that depends on the temperature ? 3.6 mv/ ? c operation stabilization wait time t amp 5 ? s
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 173 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 3.6.3 por circuit characteristics (t a = ? 40 to +105 ? c, v ss = 0 v) parameter symbol conditions min. typ. max. unit v por power supply rise time 1.45 1.51 1.57 v detection voltage v pdr power supply fall time 1.44 1.50 1.56 v minimum pulse width t pw 300 ? s note minimum time required for a por reset when v dd exceeds below v pdr . this is also the minimum time required for a por reset from when v dd exceeds below 0.7 v to when v dd exceeds v por while stop mode is entered or the main system clock is stopped through se tting bit 0 (hiostop) and bit 7 (mstop) in the clock operation status control register (csc). t pw v por v pdr or 0.7 v supply voltage (v dd )
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 174 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 3.6.4 lvd circuit characteristics lvd detection voltage of reset mode and interrupt mode (t a = ? 40 to +105 ? c, v pdr ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit power supply rise time 3.90 4.06 4.22 v v lvd0 power supply fall time 3.83 3.98 4.13 v power supply rise time 3.60 3.75 3.90 v v lvd1 power supply fall time 3.53 3.67 3.81 v power supply rise time 3.01 3.13 3.25 v v lvd2 power supply fall time 2.94 3.06 3.18 v power supply rise time 2.90 3.02 3.14 v v lvd3 power supply fall time 2.85 2.96 3.07 v power supply rise time 2.81 2.92 3.03 v v lvd4 power supply fall time 2.75 2.86 2.97 v power supply rise time 2.70 2.81 2.92 v v lvd5 power supply fall time 2.64 2.75 2.86 v power supply rise time 2.61 2.71 2.81 v v lvd6 power supply fall time 2.55 2.65 2.75 v power supply rise time 2.51 2.61 2.71 v detection voltage supply voltage level v lvd7 power supply fall time 2.45 2.55 2.65 v minimum pulse width t lw 300 ? s detection delay time 300 ? s lvd detection voltage of interrupt & reset mode (t a = ? 40 to +105 ? c, v pdr ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit v lvdd0 v poc2 , v poc1 , v poc0 = 0, 1, 1, falling reset voltage 2.64 2.75 2.86 v rising release reset voltage 2.81 2.92 3.03 v v lvdd1 lvis1, lvis0 = 1, 0 falling interrupt voltage 2.75 2.86 2.97 v rising release reset voltage 2.90 3.02 3.14 v v lvdd2 lvis1, lvis0 = 0, 1 falling interrupt voltage 2.85 2.96 3.07 v rising release reset voltage 3.90 4.06 4.22 v interrupt and reset mode v lvdd3 lvis1, lvis0 = 0, 0 falling interrupt voltage 3.83 3.98 4.13 v
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 175 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 3.6.5 power supply voltage rising slope characteristics (t a = ? 40 to +105 ? c, v ss = 0 v) parameter symbol conditions min. typ. max. unit power supply voltage rising slope s vdd 54 v/ms caution make sure to keep the internal reset state by the lvd circuit or an external reset until v dd reaches the operating voltage range shown in 3.4 ac characteristics. 3.7 ram data retention characteristics ( t a = ? 40 to +105c, v ss = 0 v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.44 note 5.5 v note this depends on the por detection voltage. for a falli ng voltage, data in ram ar e retained until the voltage reaches the level that triggers a po r reset but not once it reaches t he level at which a por reset is generated. v dd stop instruction execution standby release signal (interrupt request) stop mode ram data retention v dddr operation mode
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 176 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 3.8 flash memory programming characteristics (t a = ? 40 to +105 ? c, 2.4 v ? v dd ? 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit cpu/peripheral hardware clock frequency f clk 2.4 v ? v dd ? 5.5 v 1 32 mhz number of code flash rewrites notes 1,2,3 retained for 20 years t a = 85? c note 4 1,000 retained for 1 years t a = 25? c 1,000,000 retained for 5 years t a = 85? c note 4 100,000 number of data flash rewrites notes 1,2,3 c erwr retained for 20 years t a = 85? c note 4 10,000 times notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite.the retaining years are until next rewrite after the rewrite. 2. when using flash memory programmer and renesas electronics self programming library. 3. these are the characteristics of the flash memory and the results obt ained from reliability testing by renesas electronics corporation. 4. this temperature is the average value at which data are retained. 3.9 dedicated flash memory programmer communication (uart) (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit transfer rate during serial programming 115,200 1,000,000 bps
rl78/g13 3. electrical specific ations (g: industrial applications t a = -40 to +105 ? c) page 177 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 3.10 timing of entry to flash memory programming modes (t a = ? 40 to +105 ? c, 2.4 v ? ev dd0 = ev dd1 ? v dd ? 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit time to complete the communication for the initial setting after the external reset is released t suinit por and lvd reset must be released before the external reset is released. 100 ms time to release the external reset after the tool0 pin is set to the low level t su por and lvd reset must be released before the external reset is released. 10 ? s ? time to hold the tool0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) t hd por and lvd reset must be released before the external reset is released. 1 ms reset tool0 <1> <2> <3> t suinit 723 s + t hd processing time 1-byte data for setting mode t su <4> <1> the low level is input to the tool0 pin. <2> the external reset is released (por and lvd reset must be released before the external reset is released.). <3> the tool0 pin is set to the high level. <4> setting of the flash memory programming mode by uart reception and complete the baud rate setting. remark t suinit : communication for the initial setting must be comple ted within 100 ms after the external reset is released during this period. t su : time to release the exte rnal reset after the tool0 pi n is set to the low level t hd : time to hold the tool0 pin at the low level a fter the external reset is released (excluding the processing time of the firmware to control the flash memory)
rl78/g13 4. package drawings page 178 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 4. package drawings 4.1 20-pin products R5F1006Aasp, r5f1006casp, r5f1006dasp, r5f1006easp r5f1016aasp, r5f1016casp, r5f1016dasp, r5f1016easp R5F1006Adsp, r5f1006cdsp, r5f1006ddsp, r5f1006edsp r5f1016adsp, r5f1016cdsp, r5f1016ddsp, r5f1016edsp R5F1006Agsp, r5f1006cgsp, r5f1006dgsp, r5f1006egsp jeita package code renesas code previous code mass (typ.) [g] p-lssop20-0300-0.65 plsp0020jc-a s20mc-65-5a4-3 0.12 ns c dm m p l u t g f e b k j detail of lead end s 20 11 11 0 a h i item b c i l m n a k d e f g h j p t millimeters 0.65 (t.p.) 0.475 max. 0.13 0.5 6.1 0.2 0.10 6.65 0.15 0.17 0.03 0.1 0.05 0.24 1.3 0.1 8.1 0.2 1.2 + 0.08 ? 0.07 1.0 0.2 3 + 5 ? 3 0.25 0.6 0.15 u note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. 2012 renesas electronics corporation. all rights reserved.
rl78/g13 4. package drawings page 179 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 4.2 24-pin products r5f1007aana, r5f1007cana, r5f1007dana, r5f1007eana r5f1017aana, r5f1017cana, r5f1017dana, r5f1017eana r5f1007adna, r5f1007cdna, r5f1007ddna, r5f1007edna r5f1017adna, r5f1017cdna, r5f1017ddna, r5f1017edna r5f1007agna, r5f1007cgna, r5f1007dgna, r5f1007egna s y e lp s x b a b m a d e 18 12 13 6 7 1 24 a s b a d e 19 detail of a part expos ed die pad jeita packa g e code renes a s code previou s code ma ss (typ.)[g] p-hwqfn24-4x4-0.50 pwqn0024ke-a p24k 8-50-cab-3 0.04 6 1 18 13 7 12 19 24 index area 2 2 d a lp 0.20 2.50 0.40 4.00 4.00 2.50 refer ance symbol min nom m ax dimension in millimeters 0.30 0.30 0.50 b 0.18 x a 0.80 y 0.05 0.00 0.25 e z z c d e 1 d e 2 2 2 e 0.50 0.05 0.75 0.75 0.15 0.25 a 1 c 2 4.05 3.95 4.05 3.95 z z d e
rl78/g13 4. package drawings page 180 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 4.3 25-pin products r5f1008aala, r5f1008cala, r5f1008dala, r5f1008eala r5f1018aala, r5f1018cala, r5f1018dala, r5f1018eala r5f1008agla, r5f1008cgla, r5f1008dgla, r5f1008egla jeita package code renesas code previous code mass (typ.) [g] p-wflga25-3x3-0.50 pwlg0025ka-a p25fc-50-2n2-2 0.01 (aperture of solder resist) item dimensions d e w e a b x y y1 zd ze 3.00 0.10 3.00 0.10 0.05 0.20 0.69 0.07 0.08 0.50 0.24 0.05 (unit:mm) 0.20 0.50 0.50 s y1 s a s detail of c part y sx 21x b b m e b 0.34 0.05 0.43 0.05 0.50 0.05 0.365 0.05 r0.17 0.05 r0.165 0.05 r0.215 0.05 0.365 0.05 0.50 0.05 0.33 0.05 0.43 0.05 bsw zd ze index mark b c a sa w d e 2.27 2.27 detail of d part d 1 2 ed cb a 3 4 5 (land pad) r0.12 0.05 0.33 0.05 index mark 2012 renesas electronics corporation. all rights reserved . a
rl78/g13 4. package drawings page 181 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 4.4 30-pin products r5f100aaasp, r5f100acasp, r5f100adasp, r5f100aeasp, r5f100afasp, r5f100agasp r5f101aaasp, r5f101acasp, r5f101adasp, r5f101aeasp, r5f101afasp, r5f101agasp r5f100aadsp, r5f100acdsp, r5f100addsp, r5f100aedsp, r5f100afdsp, r5f100agdsp r5f101aadsp, r5f101acdsp, r5f101addsp, r5f101aedsp, r5f101afdsp, r5f101agdsp r5f100aagsp, r5f100acgsp, r5f100adgsp, r5f100aegsp, r5f100afgsp, r5f100aggsp jeita package code renesas code previous code mass (typ.) [g] p-lssop30-0300-0.65 plsp0030jb-b s30mc-65-5a4-3 0.18 s s h j t i g d e f c b k p l u n item b c i l m n a k d e f g h j p 30 16 11 5 a detail of lead end m m t millimeters 0.65 (t.p.) 0.45 max. 0.13 0.5 6.1 0.2 0.10 9.85 0.15 0.17 0.03 0.1 0.05 0.24 1.3 0.1 8.1 0.2 1.2 + 0.08 ? 0.07 1.0 0.2 3 + 5 ? 3 0.25 0.6 0.15 u note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. 2012 renesas electronics corporation. all rights reserved.
rl78/g13 4. package drawings page 182 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 4.5 32-pin products r5f100baana, r5f100bcana, r5f100bdana, r5f100beana, r5f100bfana, r5f100bgana r5f101baana, r5f101bcana, r5f101bdana, r5f101beana, r5f101bfana, r5f101bgana r5f100badna, r5f100bcdna, r5f100bddna, r5f100bedna, r5f100bfdna, r5f100bgdna r5f101badna, r5f101bcdna, r5f101bddna, r5f101bedna, r5f101bfdna, r5f101bgdna r5f100bagna, r5f100bcgna, r5f100bdgna, r5f100begna, r5f100bfgna, r5f100bggna 2013 renesas electronics corporation. all rights reserved . s y e lp sxb a b m a d e 24 16 17 8 9 1 32 a s b a d e 25 exposed die p ad p-hwqfn32-5x5-0.50 pwqn0032kb-a p32k8-50-3b4-5 0.06 8 1 9 16 25 32 index area 2 2 d a lp 0.20 3.50 0.40 5.00 5.00 3.50 referance symbol min nom max dimension in millimeters 0.30 0.30 0.50 b 0.18 x a 0.80 y 0.05 0.00 0.25 e z z c d e 1 d e 2 2 2 e 0.50 0.05 0.75 0.75 0.15 0.25 a 1 c 2 5.05 4.95 5.05 4.95 z z d e 17 24 jeita package code renesas code previous code mass (typ.)[g] detail of a part
rl78/g13 4. package drawings page 183 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 4.6 36-pin products r5f100caala, r5f100ccala, r5f100cdala, r5f100ceala, r5f100cfala, r5f100cgala r5f101caala, r5f101ccala, r5f101cdala, r5f101ceala, r5f101cfala, r5f101cgala r5f100cagla, r5f100ccgla, r5f100cdgla, r5f100cegla, r5f100cfgla, r5f100cggla jeita package code renesas code previous code mass (typ.) [g] p-wflga36-4x4-0.50 pwlg0036ka-a p36fc-50-aa4-2 0.023 item dimensions d e w e a b x y y1 zd ze 4.00 0.10 4.00 0.10 0.05 0.20 0.69 0.07 0.08 0.50 0.24 0.05 (unit:mm) 0.20 0.75 0.75 s y1 s a s y sx 32x b a b m e s wb zd ze index mark b c a s wa d e e 1 2 e f dc b a 3 4 5 6 c d detail detail e detail b 0.34 0.05 0.55 0.70 0.05 0.55 0.05 0.70 0.05 0.55 0.05 0.75 0.75 0.55 0.55 r0.17 0.05 r0.17 0.05 r0.12 0.05 r0.12 0.05 r0.275 0.05 r0.35 0.05 0.75 0.55 0.05 0.70 0.05 0.55 0.75 0.55 0.05 0.70 0.05 (land pad) (aperture of solder resist) d 2.90 2.90 2012 renesas electronics corporation. all rights reserved.
rl78/g13 4. package drawings page 184 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 4.7 40-pin products r5f100eaana, r5f100ecana, r5f 100edana, r5f100eeana, r5f100ef ana, r5f100egana, r5f100ehana r5f101eaana, r5f101ecana, r5f101edana, r5f101eeana, r5f101efana, r5f101egana, r5f101ehana r5f100eadna, r5f100ecdna, r5f100eddna, r5f100eedna, r5f100efdna, r5f100egdna, r5f100ehdna r5f101eadna, r5f101ecdna, r5f101eddna, r5f101eedna, r5f101efdna, r5f101egdna, r5f101ehdna r5f100eagna, r5f100ecgna, r5f100edgna, r5f100eegna, r5f100efgna, r5f100eggna, r5f100ehgna 2013 renesas electronics corporation. all rig hts res erved. s y e lp s x b a b m a d e 30 20 21 10 11 1 40 a s b a d e 31 detail of a part expos ed die pad p-hwqfn40-6x6-0.50 p40k8 -50-4b4-5 0.09 10 1 11 20 31 40 index area 2 2 d a lp 0.20 4.50 0.40 6.00 6.00 4.50 refer ance symbol min nom m ax dimension in millimeters 0.30 0.30 0.50 b 0.18 x a 0.80 y 0.05 0.00 0.25 e z z c d e 1 d e 2 2 2 e 0.50 0.05 0.75 0.75 0.15 0.25 a 1 c 2 6.05 5.95 6.05 5.95 z z d e 21 30 jeita packa g e code rene s a s code previou s code ma ss (typ.) [g ] pwqn0040kc-a
rl78/g13 4. package drawings page 185 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 4.8 44-pin products r5f100faafp, r5f100fcafp, r5f100fdafp, r5f100feafp, r5f100ffafp, r5f100fgafp, r5f100fhafp, r5f 100fjafp, r5f100f kafp, r5f100flafp r5f101faafp, r5f101fcafp, r5f101fdafp, r5f101feafp, r5f101ffafp, r5f101fgafp, r5f101fhafp, r5f 101fjafp, r5f101f kafp, r5f101flafp r5f100fadfp, r5f100fcdfp, r5f100fddfp, r5f100fedfp, r5f100ffdfp, r5f100fgdfp, r5f100fhdfp, r5f100fjdfp, r5f100fkdfp, r5f100fldfp r5f101fadfp, r5f101fcdfp, r5f101fddfp, r5f101fedfp, r5f101ffdfp, r5f101fgdfp, r5f101fhdfp, r5f101fjdfp, r5f101fkdfp, r5f101fldfp r5f100fagfp, r5f100fcgfp, r5f100fdgfp, r5f100fegfp, r5f100ffgfp, r5f100fggfp, r5f100fhgfp, r5f100fjgfp jeita package code renesas code previous code mass (typ.) [g] p-lqfp44-10x10-0.80 plqp0044gc-a p44gb-80-ues-2 0.36 s y e sxb m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 + 0.055 ? 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 10.00 0.20 10.00 0.20 12.00 0.20 12.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.80 0.20 0.10 1.00 1.00 l lp l1 0.50 0.60 0.15 1.00 0.20 3 + 5 ? 3 note each lead centerline is located within 0.20 mm of its true position at maximum material condition. detail of lead end 0.37 + 0.08 ? 0.07 b 11 22 1 44 12 23 34 33 2012 renesas electronics corporation. all rights reserved.
rl78/g13 4. package drawings page 186 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 4.9 48-pin products r5f100gaafb, r5f100gcafb, r5f100gdafb, r5f100geafb, r5f100gfafb, r5f100ggafb, r5f100ghafb, r5f100gjafb, r5f100gkafb, r5f100glafb r5f101gaafb, r5f101gcafb, r5f101gdafb, r5f101geafb, r5f101gfafb, r5f101ggafb, r5f101ghafb, r5f101gjafb, r5f101gkafb, r5f101glafb r5f100gadfb, r5f100gcdfb, r5f100gddfb, r5f100gedfb, r5f100g fdfb, r5f100ggdfb, r5f100ghdfb, r5f100gjdfb, r5f100gkdfb, r5f100gldfb r5f101gadfb, r5f101gcdfb, r5f101gddfb, r5f101gedfb, r5f101g fdfb, r5f101ggdfb, r5f101ghdfb, r5f101gjdfb, r5f101gkdfb, r5f101gldfb r5f100gagfb, r5f100gcgfb, r5f100gdgfb, r5f100gegfb, r5f100gfgfb, r5f100gggfb, r5f100ghgfb, r5f100gjgfb jeita package code renesas code previous code mass (typ.) [g] p-lfqfp48-7x7-0.50 plqp0048kf-a p48ga-50-8eu-1 0.16 s y e sxb m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 + 0.055 ? 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 7.00 0.20 7.00 0.20 9.00 0.20 9.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 0.75 0.75 l lp l1 0.50 0.60 0.15 1.00 0.20 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.22 0.05 b 12 24 1 48 13 25 37 36 2012 renesas electronics corporation. all rights reserved.
rl78/g13 4. package drawings page 187 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 r5f100gaana, r5f100gcana, r5f100gdana, r5f100geana, r5f100gfana, r5f100ggana, r5f100ghana, r5f100gjana, r5f100gkana, r5f100glana r5f101gaana, r5f101gcana, r5f101gdana, r5f101geana, r5f101gfana, r5f101ggana, r5f101ghana, r5f101gjana, r5f101gkana, r5f101glana r5f100gadna, r5f100gcdna, r5f100gddna, r5f100gedna, r5f100gfdna, r5f100ggdna, r5f100ghdna, r5f100gjdna, r5f100gkdna, r5f100gldna r5f101gadna, r5f101gcdna, r5f101gddna, r5f101gedna, r5f101gfdna, r5f101ggdna, r5f101ghdna, r5f101gjdna, r5f101gkdna, r5f101gldna r5f100gagna, r5f100gcgna, r5f100gdgna, r5f100gegna, r5f100gfgna, r5f100gggna, r5f100ghgna, r5f100gjgna 2013 renesas electronics corporation. all ri g hts res erved. s y e lp s x b a b m a d e 36 24 25 12 13 1 48 a s b a d e 37 detail of a part expos ed die pad jeita packa g e code renes a s code previou s code ma ss (typ.)[g] p-hwqfn48 -7x7-0.50 pwqn0048kb-a 48pjn-a 0.13 12 1 13 24 37 48 index area 2 2 d a lp 0.20 5.50 0.40 7.00 7.00 5.50 refer ance symbol min nom m ax dimension in millimeters 0.30 0.30 0.50 b 0.18 x a 0.80 y 0.05 0.00 0.25 e z z c d e 1 d e 2 2 2 e 0.50 0.05 0.75 0.75 0.15 0.25 a 1 c 2 7.05 6.95 7.05 6.95 z z d e 25 36 p48k8-50-5b4-6
rl78/g13 4. package drawings page 188 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 4.10 52-pin products r5f100jcafa, r5f100jdafa, r5f100jeafa, r5f100jf afa, r5f100jgafa, r5f100jhafa, r5f100jjafa, r5f100jkafa, r5f100jlafa r5f101jcafa, r5f101jdafa, r5f101jeafa, r5f101jf afa, r5f101jgafa, r5f101jhafa, r5f101jjafa, r5f101jkafa, r5f101jlafa r5f100jcdfa, r5f100jddfa, r5f100jedfa, r5f100 jfdfa, r5f100jgdfa, r5 f100jhdfa, r5f100jjdfa, r5f100jkdfa, r5f100jldfa r5f101jcdfa, r5f101jddfa, r5f101jedfa, r5f101 jfdfa, r5f101jgdfa, r5 f101jhdfa, r5f101jjdfa, r5f101jkdfa, r5f101jldfa r5f100jcgfa, r5f100jdgfa, r5f 100jegfa, r5f100jfgfa, r5f100j ggfa, r5f100jhgfa, r5f100jjgfa y e x b m l c hd he a1 a2 a d e item dimen s ions d e hd he a a1 a2 1.40 c e x y 0.65 0.13 0.10 l detail of lead end b 13 26 1 52 14 27 40 39 2 1 3 0.3 p-lqfp52-10x10-0.65 jeita p ack a ge code renesas code plqp0052ja-a previo us code p52gb-65-gbs-1 mass (typ.) [g] note 1.dimens ions ? 1? a nd ? 2? do not inclu de mold flash. 2.dimens ion ? 3? does not inclu de trim off s et. 2012 renesas electronics corporation. all rights reserved. (unit:mm) 10.00 0.10 10.00 0.10 12.00 0.20 12.00 0.20 1.70 max. 0.10 0.05 0.32 0.05 0.145 0.055 0.50 0.15 0 to 8
rl78/g13 4. package drawings page 189 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 4.11 64-pin products r5f100lcafa, r5f100ldafa, r5f 100leafa, r5f100lfafa, r5f100lgafa, r5f100lhafa, r5f100ljafa, r5f100lkafa, r5f100llafa r5f101lcafa, r5f101ldafa, r5f 101leafa, r5f101lfafa, r5f101lgafa, r5f101lhafa, r5f101ljafa, r5f101lkafa, r5f101llafa r5f100lcdfa, r5f100lddfa, r5f100ledfa, r5f100lf dfa, r5f100lgdfa, r5f100lhdfa, r5f100ljdfa, r5f100lkdfa, r5f100lldfa r5f101lcdfa, r5f101lddfa, r5f101ledfa, r5f101lf dfa, r5f101lgdfa, r5f101lhdfa, r5f101ljdfa, r5f101lkdfa, r5f101lldfa r5f100lcgfa, r5f100ldgfa, r5f100legfa , r5f100lfgfa, r5f100lggfa, r5f100lhgfa, r5f100ljgfa jeita package code renesas code previous code mass (typ.) [g] p-lqfp64-12x12-0.65 plqp0064ja-a p64gk-65-uet-2 0.51 note each lead centerline is located within 0.13 mm of its true position at maximum material condition. detail of lead end l c lp hd he zd ze l1 a1 a2 a d e 16 32 1 64 17 33 49 48 s y e sxb m a3 s 0.145 + 0.055 ? 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 12.00 0.20 12.00 0.20 14.00 0.20 14.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.65 0.13 0.10 1.125 1.125 l lp l1 0.50 0.60 0.15 1.00 0.20 3 + 5 ? 3 0.32 + 0.08 ? 0.07 b 2012 renesas electronics corporation. all rights reserved.
rl78/g13 4. package drawings page 190 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 r5f100lcafb, r5f100ldafb, r5f 100leafb, r5f100lfafb, r5f100lgafb, r5f100lhafb, r5f100ljafb, r5f100lkafb, r5f100llafb r5f101lcafb, r5f101ldafb, r5f101leafb, r5f101lfafb, r5f101l gafb, r5f101lhafb, r5f101ljafb, r5f101lkafb, r5f101llafb r5f100lcdfb, r5f100lddfb, r5f100ledfb, r5f100lf dfb, r5f100lgdfb, r5f100lhdfb, r5f100ljdfb, r5f100lkdfb, r5f100lldfb r5f101lcdfb, r5f101lddfb, r5f101ledfb, r5f101lfdfb, r5f101lg dfb, r5f101lhdfb, r5f101ljdfb, r5f101lkdfb, r5f101lldfb r5f100lcgfb, r5f100ldgfb, r5f100legfb, r5f100lfgfb, r5f100l ggfb, r5f100lhgfb, r5f100ljgfb jeita package code renesas code previous code mass (typ.) [g] p-lfqfp64-10x10-0.50 plqp0064kf-a p64gb-50-ueu-2 0.35 s y e sxb m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 + 0.055 ? 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 10.00 0.20 10.00 0.20 12.00 0.20 12.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 0.15 1.00 0.20 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.22 0.05 b 16 32 1 64 17 33 49 48 2012 renesas electronics corporation. all rights reserved.
rl78/g13 4. package drawings page 191 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 r5f100lcabg, r5f100ldabg, r5f100leabg, r5f100lfabg, r5f100 lgabg, r5f100lhabg, r5f100ljabg r5f101lcabg, r5f101ldabg, r5f101leabg, r5f101lfabg, r5f101 lgabg, r5f101lhabg, r5f101ljabg r5f100lcgbg, r5f100ldgbg, r5f100legb g, r5f100lfgbg, r5f100lggbg, r5f100lhgbg, r5f100ljgbg jeita package code renesas code previous code mass (typ.) [g] p-vfbga64-4x4-0.40 pvbg0064la-a p64f1-40-aa2-2 0.03 item dimensions d e w a a1 a2 e 4.00 0.10 4.00 0.10 0.40 0.05 0.08 0.20 0.60 0.60 0.15 0.20 0.05 0.05 0.89 0.10 0.69 0.25 (unit:mm) x y y1 zd ze b zd ze a index mark a2 a1 e s w a s wb b a s y s y1 s s x ba b m 8 7 6 5 4 3 2 1 abcd e fgh d e index mark 2012 renesas electronics corporation. all rights reserved.
rl78/g13 4. package drawings page 192 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 4.12 80-pin products r5f100mfafa, r5f100mgafa, r5f100mhafa, r5f100mjafa, r5f100mkafa, r5f100mlafa r5f101mfafa, r5f101mgafa, r5f101mhafa, r5f101mjafa, r5f101mkafa, r5f101mlafa r5f100mfdfa, r5f100mgdfa, r5f100mhdfa, r5f100mjdfa, r5f100mkdfa, r5f100mldfa r5f101mfdfa, r5f101mgdfa, r5f101mhdfa, r5f101mjdfa, r5f101mkdfa, r5f101mldfa r5f100mfgfa, r5f100mggfa, r5f100mhgfa, r5f100mjgfa renesas code p-lqfp80-14x14-0.65 plqp0080jb-e 0.69 d e hd he a a2 bp c lp x l1 0.13 0.886 14.00 14.00 1.40 min nom max dimension in millimeters a1 0.05 1.35 0.26 1.70 0.20 1.45 0.38 13.80 13.80 14.20 14.20 0.10 0.20 e 0.736 1.036 0 8 a3 0.25 0.125 0.32 0.145 l 0.80 1.40 1.80 zd 0.825 ze 0.825 3 y s y e s x bp m l c lp hd he zd ze l1 a1 a2 a e a3 s detail of lead end 20 40 1 80 21 41 d a b ab 61 60 p80gc-65-ubt -2 previous code mass (typ .) [g] jeita package code referance symbol 17.00 17.20 17.20 17.40 17.00 17.40 1.60 0.65 0.10 2012 renesas electronicscorporation. all rights reserved.
rl78/g13 4. package drawings page 193 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 r5f100mfafb, r5f100mgafb, r5f100mhafb, r5f100mjafb, r5f100mkafb, r5f100mlafb r5f101mfafb, r5f101mgafb, r5f101mhafb, r5f101mjafb, r5f101mkafb, r5f101mlafb r5f100mfdfb, r5f100mgdfb, r5f100mhdfb, r5f100mjdfb, r5f100mkdfb, r5f100mldfb r5f101mfdfb, r5f101mgdfb, r5f101mhdfb, r5f101mjdfb, r5f101mkdfb, r5f101mldfb r5f100mfgfb, r5f100mggfb, r5f100mhgfb, r5f100mjgfb jeita package code renesas code previous code mass (typ.) [g] p-lfqfp80-12x12-0.50 plqp0080ke-a p80gk-50-8eu-2 0.53 s y e sxb m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 + 0.055 ? 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 12.00 0.20 12.00 0.20 14.00 0.20 14.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 0.15 1.00 0.20 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.22 0.05 b 20 40 1 80 21 41 61 60 2012 renesas electronics corporation. all rights reserved.
rl78/g13 4. package drawings page 194 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 4.13 100-pin products r5f100pfafb, r5f100pg afb, r5f100phafb, r5f100pjafb, r5f100pkafb, r5f100plafb r5f101pfafb, r5f101pg afb, r5f101phafb, r5f101pjafb, r5f101pkafb, r5f101plafb r5f100pfdfb, r5f100pgdfb, r5f100phdfb, r5f100pjdfb, r5f100pkdfb, r5f100pldfb r5f101pfdfb, r5f101pgdfb, r5f101phdfb, r5f101pjdfb, r5f101pkdfb, r5f101pldfb r5f100pfgfb, r5f100pggfb, r5f100phgfb, r5f100pjgfb s y e sxb m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 (unit:mm) item dimensions d e hd he a a1 a2 a3 14.00 0.20 14.00 0.20 16.00 0.20 16.00 0.20 1.60 max. 0.10 0.05 1.40 + + 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.00 1.00 l lp l1 0.50 0.60 0.15 1.00 0.20 3 3 5 detail of lead end 0.22 0.055 0.045 b 25 50 1 100 26 51 75 76 0.05 a b ab jeita package code renesas code previous code mass (typ.) [g] p-lfqfp100-14x14-0.50 plqp0100ke-a p100gc-50-gbr-1 0.69 2012 renesas electronics corporation. all rights reserved.
rl78/g13 4. package drawings page 195 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 r5f100pfafa, r5f100pg afa, r5f100phafa, r5f100pjafa, r5f100pkafa, r5f100plafa r5f101pfafa, r5f101pg afa, r5f101phafa, r5f101pjafa, r5f101pkafa, r5f101plafa r5f100pfdfa, r5f100pgdfa, r5f100phdfa, r5f100pjdfa, r5f100pkdfa, r5f100pldfa r5f101pfdfa, r5f101pgdfa, r5f101phdfa, r5f101pjdfa, r5f101pkdfa, r5f101pldfa r5f100pfgfa, r5f100pggfa, r5f100phgfa, r5f100pjgfa b s y e sxb m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 (unit:mm) item dimensions d e hd he a a1 a2 a3 20.00 0.20 14.00 0.20 22.00 0.20 16.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.07 0.08 0.055 0.045 0.25 c e x y zd ze 0.65 0.13 0.10 0.575 0.825 l lp l1 0.50 0.60 0.15 5 3 1.00 0.20 3 detail of lead end 0.32 b + + + 30 50 1 100 31 51 81 80 a ab jeita package code renesas code previous code mass (typ.) [g] p-lqfp100-14x20-0.65 plqp0100jc-a p100gf-65-gbn-1 0.92 2012 renesas electronics corporation. all rights reserved.
rl78/g13 4. package drawings page 196 of 196 r01ds0131ej0330 rev.3.30 mar 31, 2016 4.14 128-pin products r5f100shafb, r5f100sjafb, r5f100skafb, r5f100slafb r5f101shafb, r5f101sjafb, r5f101skafb, r5f101slafb r5f100shdfb, r5f100sjdfb, r5f100skdfb, r5f100sldfb r5f101shdfb, r5f101sjdfb, r5f101skdfb, r5f101sldfb s y e sxb m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 (unit:mm) item dimensions d e hd he a a1 a2 a3 20.00 0.20 14.00 0.20 22.00 0.20 16.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 0.75 0.75 l lp l1 0.50 0.60 0.15 1.00 0.20 detail of lead end b 38 64 1 128 39 65 102 103 0.22 3 + 5 ? 3 + 0.055 ? 0.045 0.05 a b ab 2012 renesas electronics corporation. all rights reserved. jeita package code renesas code previous code mass (typ.) [g] p-lfqfp128-14x20-0.50 plqp0128kd-a p128gf-50-gbp-1 0.92
c - 1 revision history rl78/g13 data sheet description rev. date page summary 1.00 feb 29, 2012 - first edition issued 2.00 oct 12, 2012 7 figure 1-1. part number, memory size , and package of rl78/g13: pin count corrected. 25 1.4 pin identification: description of pins intp0 to intp11 corrected. 40, 42, 44 1.6 outline of functions: descriptions of subsystem clock, low-speed on-chip oscillator, and general-purpo se register corrected. 41, 43, 45 1.6 outline of functi ons: lists of descriptions changed. 59, 63, 67 descriptions of note 8 in a table corrected. 68 (4) common to rl78/g13 all products: descriptions of notes corrected. 69 2.4 ac characteristics: symbol of external system clock frequency corrected. 96 to 98 2.6.1 a/d converter characteri stics: notes of overall error corrected. 100 2.6.2 temperature s ensor characteristics: parameter name corrected. 104 2.8 flash memory programming charac teristics: incorre ct descriptions corrected. 116 3.10 52-pin products: package draw ings of 52-pin products corrected. 120 3.12 80-pin products: package draw ings of 80-pin products corrected. 3.00 aug 02, 2013 1 modification of 1.1 features 3 modification of 1.2 list of part numbers 4 to 15 modification of table 1-1. list of or dering part numbers, note, and caution 16 to 32 modification of package type in 1.3.1 to 1.3.14 33 modification of description in 1.4 pin identification 48, 50, 52 modification of caution, table, and note in 1.6 outline of functions 55 modification of description in tabl e of absolute maximum ratings (t a = 25 ?c) 57 modification of table, note, caution, and remark in 2.2.1 x1, xt1 oscillator characteristics 57 modification of table in 2.2.2 on -chip oscillator characteristics 58 modification of note 3 of table (1 /5) in 2.3.1 pin characteristics 59 modification of note 3 of table (2 /5) in 2.3.1 pin characteristics 63 modification of table in (1) flash rom: 16 to 64 kb of 20- to 64-pin products 64 modification of notes 1 and 4 in (1) fl ash rom: 16 to 64 kb of 20- to 64-pin products 65 modification of table in (1) flash rom: 16 to 64 kb of 20- to 64-pin products 66 modification of notes 1, 5, and 6 in (1 ) flash rom: 16 to 64 kb of 20- to 64- pin products 68 modification of notes 1 and 4 in (2) fl ash rom: 96 to 256 kb of 30- to 100- pin products 70 modification of notes 1, 5, and 6 in (2) flash rom: 96 to 256 kb of 30- to 100-pin products 72 modification of notes 1 and 4 in (3) flash rom: 384 to 512 kb of 44- to 100- pin products 74 modification of notes 1, 5, and 6 in (3) flash rom: 384 to 512 kb of 44- to 100-pin products 75 modification of (4) peripheral functions (common to all products) 77 modification of table in 2.4 ac characteristics 78, 79 addition of minimum instruction execut ion time during main system clock operation 80 modification of figures of ac timing test points and external system clock timing
c - 2 description rev. date page summary 3.00 aug 02, 2013 81 modification of figure of ac timing test points 81 modification of description and note 3 in (1) during communication at same potential (uart mode) 83 modification of description in (2) during communication at same potential (csi mode) 84 modification of description in (3) during communication at same potential (csi mode) 85 modification of description in (4) during communication at same potential (csi mode) (1/2) 86 modification of description in (4) during communication at same potential (csi mode) (2/2) 88 modification of table in (5) during communication at same potential (simplified i 2 c mode) (1/2) 89 modification of table and caution in (5) during communication at same potential (simplified i 2 c mode) (2/2) 91 modification of table and notes 1 and 4 in (6) communication at different potential (1.8 v, 2.5 v, 3 v) (uart mode) (1/2) 92, 93 modification of table and notes 2 to 7 in (6) communication at different potential (1.8 v, 2.5 v, 3 v) (uart mode) (2/2) 94 modification of remarks 1 to 4 in (6) communication at different potential (1.8 v, 2.5 v, 3 v) (uart mode) (2/2) 95 modification of table in (7) communicati on at different potential (2.5 v, 3 v) (csi mode) (1/2) 96 modification of table and caution in (7) communication at different potential (2.5 v, 3 v) (csi mode) (2/2) 97 modification of table in (8) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (1/3) 98 modification of table, note 1, and caut ion in (8) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (2/3) 99 modification of table, note 1, and caut ion in (8) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (3/3) 100 modification of remarks 3 and 4 in (8) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (3/3) 102 modification of table in (9) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (1/2) 103 modification of table and caution in (9) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (2/2) 106 modification of table in (10) communicati on at different potential (1.8 v, 2.5 v, 3 v) (simplified i 2 c mode) (1/2) 107 modification of table, note 1, and caution in (10) communication at different potential (1.8 v, 2.5 v, 3 v) (simplified i 2 c mode) (2/2) 109 addition of (1) i 2 c standard mode 111 addition of (2) i 2 c fast mode 112 addition of (3) i 2 c fast mode plus 112 modification of iica serial transfer timing 113 addition of table in 2.6.1 a/ d converter characteristics 113 modification of description in 2.6.1 (1) 114 modification of notes 3 to 5 in 2.6.1 (1) 115 modification of description and not es 2, 4, and 5 in 2.6.1 (2) 116 modification of description and notes 3 and 4 in 2.6.1 (3) 117 modification of description and notes 3 and 4 in 2.6.1 (4)
c - 3 description rev. date page summary 3.00 aug 02, 2013 118 modification of table in 2.6.2 temperature sensor/internal reference voltage characteristics 118 modification of table and note in 2.6.3 por circuit characteristics 119 modification of table in 2.6. 4 lvd circuit characteristics 120 modification of table of lvd detection voltage of interrupt & reset mode 120 renamed to 2.6.5 power supply voltage rising slope characteristics 122 modification of table, figure, and rema rk in 2.10 timing specs for switching flash memory programming modes 123 modification of caution 1 and description 124 modification of table and remark 3 in absolute maximum ratings (t a = 25c) 126 modification of table, note, caution, and remark in 3.2.1 x1, xt1 oscillator characteristics 126 modification of table in 3.2.2 on -chip oscillator characteristics 127 modification of note 3 in 3.3.1 pin characteristics (1/5) 128 modification of note 3 in 3.3.1 pin characteristics (2/5) 133 modification of notes 1 and 4 in (1) fl ash rom: 16 to 64 kb of 20- to 64-pin products (1/2) 135 modification of notes 1, 5, and 6 in (1 ) flash rom: 16 to 64 kb of 20- to 64- pin products (2/2) 137 modification of notes 1 and 4 in (2) fl ash rom: 96 to 256 kb of 30- to 100- pin products (1/2) 139 modification of notes 1, 5, and 6 in (2) flash rom: 96 to 256 kb of 30- to 100-pin products (2/2) 140 modification of (3) peripheral functions (common to all products) 142 modification of table in 3.4 ac characteristics 143 addition of minimum instruction execut ion time during main system clock operation 143 modification of figure of ac timing test points 143 modification of figure of external system clock timing 145 modification of figure of ac timing test points 145 modification of description, note 1, and caution in (1) during communication at same potential (uart mode) 146 modification of description in (2) during communication at same potential (csi mode) 147 modification of description in (3) during communication at same potential (csi mode) 149 modification of table, note 1, and caution in (4) during communication at same potential (simplified i 2 c mode) 151 modification of table, note 1, and caut ion in (5) communication at different potential (1.8 v, 2.5 v, 3 v) (uart mode) (1/2) 152 to 154 modification of table, notes 2 to 6, caution, and remarks 1 to 4 in (5) communication at different potential (1 .8 v, 2.5 v, 3 v) (uart mode) (2/2) 155 modification of table in (6) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (1/3) 156 modification of table and caution in (6) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (2/3) 157, 158 modification of table, caution, and re marks 3 and 4 in (6) communication at different potential (1.8 v, 2. 5 v, 3 v) (csi mode) (3/3) 160, 161 modification of table and caution in (7) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode)
c - 4 description rev. date page summary 3.00 aug 02, 2013 163 modification of table in (8) communication at different potential (1.8 v, 2.5 v, 3 v) (simplified i 2 c mode) (1/2) 164, 165 modification of table, note 1, and caut ion in (8) communication at different potential (1.8 v, 2.5 v, 3 v) (simplified i 2 c mode) (2/2) 166 modification of table in 3.5.2 serial interface iica 166 modification of iica serial transfer timing 167 addition of table in 3.6.1 a/ d converter characteristics 167, 168 modification of table and notes 3 and 4 in 3.6.1 (1) 169 modification of description in 3.6.1 (2) 170 modification of description and note 3 in 3.6.1 (3) 171 modification of description and notes 3 and 4 in 3.6.1 (4) 172 modification of table and note in 3.6.3 por circuit characteristics 173 modification of table of lvd detection voltage of interrupt & reset mode 173 modification from supply voltage rise time to 3.6.5 power supply voltage rising slope characteristics 174 modification of 3.9 dedicated flash memory programmer communication (uart) 175 modification of table, figure, and rema rk in 3.10 timing specs for switching flash memory programming modes 3.10 nov 15, 2013 123 caution 4 added. 125 note for operating ambient temperature in 3.1 absolute maximum ratings deleted. 3.30 mar 31, 2016 modification of the position of the index mark in 25-pin plastic wflga (3 3 mm, 0.50 mm pitch) of 1.3.3 25-pin products modification of power supply voltage in 1.6 outline of functions [20-pin, 24- pin, 25-pin, 30-pin, 32-pin, 36-pin products] modification of power supply voltage in 1.6 outline of functions [40-pin, 44- pin, 48-pin, 52-pin, 64-pin products] modification of power supply voltage in 1.6 outline of func tions [80-pin, 100- pin, 128-pin products] ack corrected to ack ack corrected to ack all trademarks and registered trademarks ar e the property of their respective owners. superflash is a registered trademark of silicon storage technology, inc. in several countries including the united states and japan. caution: this product uses superflash ? technology licensed from silicon storage technology, inc.
notes for cmos devices (1) voltage application waveform at input pin: waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cm os device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an in ternal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resist or if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fi eld, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade t he device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequat e. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be gr ounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touc hed with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not necessarily define the in itial status of a mos device. immediately after the power source is turn ed on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o setti ngs or contents of registers. a device is not initialized un til the reset signal is received. a re set operation must be executed immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the po wer supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that re sults from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elem ents. input of signals during th e power off state must be judged separately for each device and according to re lated specifications governing the device.
notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics do es not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property right s of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat t o human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics, e specially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas e lectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have spec ific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or otherwis e places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesas e lectronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this documen t or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-owned subs idiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. california eastern laboratories, inc. 4590 patrick henry drive, santa clara, california 95054-1817, u.s.a. tel: +1-408-919-2500, fax: +1-408-988-0279 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-6503-0, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. room 1709, quantum plaza, no.27 zhichunlu haidian district, beijing 100191, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 301, tower a, central towers, 555 langao road, putuo district, shanghai, p. r. china 200333 tel: +86-21-2226-0888, fax: +86-21-2226-0999 renesas electronics hong kong limited unit 1601-1611, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2265-6688, fax: +852 2886-9022 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei 10543, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre, singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics malaysia sdn.bhd. unit 1207, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics india pvt. ltd. no.777c, 100 feet road, hal ii stage, indiranagar, bangalore, india tel: +91-80-67208700, fax: +91-80-67208777 renesas electronics korea co., ltd. 12f., 234 teheran-ro, gangnam-gu, seoul, 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2016 renesas electronics corporation. all rights reserved. colophon 5.0

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